Clock Select - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Quad SPI Controller CSEL Settings
Table A-17: Quad SPI Controller CSEL Pin Settings
Setting
(
osc1_clk EOSC1
pin) range
Device clock
(qspi_clk)
Controller clock
(qspi_ref_clk)
Controller baud
rate divisor (even
numbers only)
Flash read
instruction (1
dummy byte for
READ_FAST)
mpu_clk
PLL modes

Clock Select

The boot ROM reads the clock select values to determine what frequency has been selected for the CPU
clock and any interface clock during boot.
The clock select (CSEL) pins are asserted to select the speed of the HPS boot interface. If the FPGA is used
as the boot source, the CSEL pins are ignored. The CSEL values define the main PLL,
l4_sp_clk
peripheral PLL parameters and the clock dividers for clocks derived from the PLLs.
Note: The terms CSEL and CLKSEL are used interchangeably in Altera documentation to refer to clock
select.
Note: At power-up or reset, when
HPS PLLs are in bypass mode. Thus, HPS user clocks exported to the FPGA fabric run at
frequency.
I/O Configuration
The flash devices needed for booting must be connected to specific I/Os. The Boot ROM configures these
I/Os depending on the flash device selected by boot select setting. To configure the I/Os, the boot ROM
performs pin muxing and pin configuration on these I/Os.
On cold reset, the boot ROM always configures the pin muxes and pin configurations. On warm reset, the
user has the capability to specify whether or not the boot ROM code configures the I/Os and pin muxes
(73) Not applicable when on WARM reset.
Booting and Configuration
Send Feedback
(73)
0
10–50 MHz
/4,
osc1_clk
12.5 MHz max
, 50 MHz
osc1_clk
max
4
READ
, 50 MHz
osc1_clk
max
Bypassed
. Based on the clock source and clock select settings, boot ROM configures the main PLL and
CSEL[1:0]
CSEL[1:0] Pin Value
1
20–50 MHz 25–50 MHz
/2, 25 MHz
osc1_clk osc1_clk
max max
*2,
osc1_clk osc1_clk
100 MHz max 200 MHz max
4 4
READ READ_FAST
*8,
osc1_clk osc1_clk
400 MHz max 400 MHz max
Locked Locked
=0x0 or
BSEL[2:0]
Quad SPI Controller CSEL Settings
2
10–25 MHz
*1, 50 MHz
osc1_clk
50 MHz max
*4,
osc1_clk
200 MHz max
4
READ_FAST
*8,
osc1_clk
400 MHz max
Locked
l2_mp_clk
is configured to boot from FPGA, the
A-25
3
*2,
*8,
*16,
and
osc1_clk
Altera Corporation