Rate Match Fifo Operation In Basic Mode; Additional Options In Basic Mode - Altera Cyclone IV Device Handbook

1–50
Figure 1–46. Transceiver Configurations in Basic Mode with a 10-Bit Wide PMA-to-PCS Interface
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner
Manual Alignment
(Pattern Length)
(7-Bit, 10-Bit)
8B/10B
Disabled
Encoder/Decoder
Rate Match FIFO
Disabled
Byte SERDES
Disabled Enabled
0.6- 0.6-
Data Rate (Gbps)
1.25 2.5
0.6- 0.6-
1.5625 3.125
Byte Ordering
Disabled Disabled
FPGA Fabric-to-
Transceiver
10-Bit 20-Bit
Interface Width
FPGA Fabric-to-
60- 30-
Transceiver
125 125
Interface
60- 30-
156.25 156.25
Fredquency (MHz)

Rate Match FIFO Operation in Basic Mode

In Basic mode, the rate match FIFO performs the following operations:
Deletes a maximum of four skip patterns from a cluster, if there is one skip pattern
■
left in the cluster after deletion
■ Insert a maximum of four skip patterns in a cluster, if there are less than five skip
patterns in the cluster after deletion
■ Automatically deletes the data byte that causes the FIFO to go full and asserts the
rx_rmfifofull flag synchronous to the subsequent data byte
Automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to
■
go empty and asserts the rx-fifoempty flag synchronous to the inserted /K30.7/
(9'h1FE)

Additional Options in Basic Mode

In Basic mode, the transceiver supports the following additional options:
■ low-latency PCS operation
Cyclone IV Device Handbook,
Volume 2
Disabled
Bit Slip
(7-Bit, 10-Bit)
Enabled Disabled Enabled
Disabled Disabled Disabled
Disabled Enabled Disabled Enabled Disabled Enabled
0.6- 0.6- 0.6- 0.6- 0.6-
1.25 2.5 1.25 2.5 1.25
0.6- 0.6- 0.6- 0.6- 0.6-
1.5625 3.125 1.5625 3.125 1.5625
Disabled Disabled Disabled Disabled Disabled
8-Bit 16-Bit 10-Bit 20-Bit 8-Bit
60- 30- 60- 30- 60-
125 125 125 125 125
60- 30- 60- 30- 60-
156.25 156.25 156.25 156.25 156.25
Applicable for devices in
F324 and smaller packages
Chapter 1: Cyclone IV Transceivers Architecture
Basic (10-Bit PMA-PCS Interface Width)
×1, ×2, ×4
Automatic Synchronization
State Machine (7-Bit, 10-Bit)
Disabled
Disabled Disabled
Disabled Enabled Disabled
0.6- 0.6- 0.6- 0.6-
2.5 1.25 2.5 1.25
0.6- 0.6- 0.6- 0.6-
3.125 1.5625 3.125 1.5625
Disabled Disabled Disabled Disabled Disabled
16-Bit 10-Bit 20-Bit 8-Bit
30- 60- 30- 60-
125 125 125 125
30- 60- 30- 60-
156.25 156.25 156.25 156.25 156.25
Applicable for devices in
F484 and larger packages
Transceiver Functional Modes
Enabled
Disabled
Enabled Disabled
Enabled Disabled
Enabled Disabled Enabled Disabled
0.6- 0.6- 0.6- 0.6-
2.5 1.25 2.5 1.25
0.6- 0.6- 0.6- 0.6-
3.125 1.5625 3.125 1.5625
Enabled Disabled Disabled Disabled Disabled
16-Bit 16-Bit 8-Bit 16-Bit 10-Bit
30- 30- 60- 30- 60-
125 125 125 125 125
30- 30- 60- 30- 60-
156.25 156.25 156.25 156.25
February 2015 Altera Corporation
Enabled
0.6-
2.5
0.6-
3.125
20-Bit
30-
125
30-
156.25