Boot Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Figure A-4: HPS Boots From FPGA
In the figure below, the FPGA is configured first through one of its non-HPS configuration sources and
then the HPS executes the preloader from the FPGA. In this situation, the HPS should not be released
from reset until the FPGA is powered on and programmed. Once the FPGA is in user mode and the HPS
has been released from reset, the boot ROM code begins executing. The HPS boot ROM code executes the
preloader from the FPGA fabric over the HPS-to-FPGA bridge.
Configuration

Boot Definitions

The following sections contain basic terms and definitions that are part of the boot process.
Reset
Reset precedes the boot stages and is an important part of device initialization. There are two different
reset types: cold reset and warm reset.
The boot process begins when the CPU in the MPU exits from the reset state. When the CPU exits from
reset, it starts executing code at the reset exception address where the boot ROM code is located.
With warm reset, some software registers are preserved and the boot process may skip some steps
depending on software settings. In addition, on a warm reset, the preloader has the ability to be executed
from on-chip RAM.
Boot ROM
The boot ROM code is 64 KB in size and located in on-chip ROM at address range 0xFFFD0000 to
0xFFFDFFFF. The function of the boot ROM code is to determine the boot source, initialize the HPS after
a reset, and jump to the preloader. In the case of indirect execution, the boot ROM code loads the
Booting and Configuration
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FPGA Portion
PCIe
Active Serial/
Boot &
Active Serial x4
Sources
Passive
Serial
Passive
Parallel
Altera SoC Device
HPS Portion
MPU
FPGA
HPS-to-FPGA
Fabric
Bridge
Boot
ROM
A-5
Boot Definitions
Altera Corporation