Boot Select - Altera cyclone V Technical Reference

A-6

Boot Select

preloader image from the flash memory to on-chip RAM. The boot ROM performs the following actions
to initialize the HPS:
• Enable instruction cache, branch predictor, floating point unit, NEON vector unit of CPU0
• Sets up the level 4 (L4) watchdog 0 timer
• Configures the main PLL and peripheral PLL based on the CSEL value
• Initializes the flash controller to default settings
When booting from flash memory, the boot ROM code uses the top 4 KB of the on-chip RAM as data
workspace. This area is reserved for the boot ROM code after a reset until the boot ROM code passes
software control to preloader. For a warm RAM boot or a cold boot from FPGA, the boot ROM code does
not reserve the top 4 KB of the on-chip RAM, and the user may place user data in this area without being
overwritten by boot ROM.
The boot process begins when CPU0 exits from the reset state. The boot ROM code only executes on
CPU0. CPU1 is held in reset while boot ROM executes on CPU0. When a CPU0 exits from reset, it starts
executing code at the reset exception address.
When CPU0 exits the boot ROM code and starts executing user software, the boot ROM access is
disabled. The user software in CPU0 must map the user software exception vectors at 0x0 (which is
previously mapped to boot ROM exception vectors). The user software also has the option of releasing
CPU1 from reset. If CPU1 is released from reset, CPU1 executes the user software exception instead of
boot ROM.
Boot Select
The boot select (BSEL) pins offer multiple methods to obtain the preloader image. On a cold reset or when
a RAM boot has not been requested, the user asserts the BSEL pins on the device to indicate the boot
source that is required. These pins are sampled on deassertion of cold reset and are written to the
bootinfo
that the appropriate interface pins can be initialized. If the boot source is from FPGA, the
reads as 0x1 in the
Note: The acronyms BSEL and BOOTSEL are used interchangeably to define the boot select pins.
Table A-1: BSEL Values for Boot Source Selection
0x0
0x1
0x2
0x3
0x4
0x5
Altera Corporation
register in the System Manager. The value of this register is read during boot ROM execution so
register and no HPS interface is configured for external boot.
bootinfo
BSEL[2:0] Value Flash Device
Reserved
FPGA (HPS-to-FPGA bridge)
1.8 V NAND flash memory
3.3 V NAND flash memory
1.8 V SD/​MMC flash memory with external
transceiver
3.3 V SD/​MMC flash memory with internal
transceiver
cv_5v4
2016.10.28
field value
bsel
Booting and Configuration
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