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No.
Name
High-speed counter settings
400
(X0-X3)
High-speed counter settings
401
(X4-X7)
(Note 1): When the high-speed counter CH0, CH2, CH4 and CH6 are set to one of 2-phase, individual and direction
distinction, the setting of CH1, CH3, CH5 and CH7 are invalid.
(Note 2): The high-speed counter hardware reset input can only use CH0 and CH2. X6 and X7 can be allocated for
CH0 and CH2 respectively.
(Note 3): When the same input is set to one of high-speed counter, pulse catch and interrupt input, the priority order is
high-speed counter → pulse catch → interrupt input.
Initial value
Sets value range and description
Not set X0 as High-speed counter
CH0:
addition input (X0)
Not set X0 as
subtraction input (X0)
High-speed
2-phase input (X0, X1)
counter
one input (X0, X1)
direction distinction (X0, X1)
CH1:
Not set X1 as High-speed counter
Not set X1 as
addition input (X1)
High-speed
subtraction input (X1)
counter
Not set X2 as High-speed counter
CH2:
addition input (X2)
Not set X2 as
subtraction input (X2)
High-speed
2-phase input (X2, X3)
counter
one input (X2, X3)
direction distinction (X2, X3)
CH3:
Not set X3 as High-speed counter
Not set X3 as
addition input (X3)
High-speed
subtraction input (X3)
counter
Not set X4 as High-speed counter
CH4:
addition input (X4)
Not set X4 as
subtraction input (X4)
High-speed
2-phase input (X4, X5)
counter
one input (X4, X5)
direction distinction (X4, X5)
CH5:
Not set X5 as High-speed counter
Not set X5 as
addition input (X5)
High-speed
subtraction input (X5)
counter
Not set X6 as High-speed counter
addition input (X6)
CH6:
subtraction input (X6)
Not set X6 as
2-phase input (X6, X7)
High-speed
one input (X6, X7)
counter
direction distinction (X6, X7)
Reset input of the high-speed counter CH0
CH7:
Not set X7 as High-speed counter
Not set X7 as
addition input (X7)
High-speed
subtraction input (X7)
counter
reset input of high-speed counter CH2
26.5 Table of System Registers
26-61
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