Cl6 - Cache Line Size; Hdr6 - Header Type; Cl6 - Cache Line Size Register; Hdr6 - Header Type Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

6.2.7

CL6 - Cache Line Size

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 30.

CL6 - Cache Line Size Register

Default
Bit Access
Value
7:0 RW
6.2.8

HDR6 - Header Type

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Regos t
Table 31.

HDR6 - Header Type Register

Bit Access Default
Value
7:0 RO
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
90
RST/
PWR
00h Core Cache Line Size (Scratch pad)
Implemented by PCI Express devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI
Express device functionality.
RST/
PWR
01h Core Header Type Register (HDR)
Returns 01 to indicate that this is a single function device with
bridge header layout.
®
Celeron
Processor Configuration Registers
0/6/0/PCI
Ch
00h
RW
8 bits
Description
0/6/0/PCI
Eh
01h
RO
8 bits
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002