Cl1-Cache Line Size Register; Hdr1-Header Type Register; Pbusn1-Primary Bus Number Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.7 CL1—Cache Line Size Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
2.6.8 HDR1—Header Type Register
This register identifies the header layout of the configuration space. No physical
register exists at this location.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
2.6.9 PBUSN1—Primary Bus Number Register
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
7:0
90
0/1/0–2/PCI
Ch
00h
RW
8 bits
Reset RST/
Attr
Value PWR
RW 00h Uncore
0/1/0–2/PCI
Eh
81h
RO
8 bits
Reset RST/
Attr
Value PWR
RO 81h Uncore
0/1/0–2/PCI
18h
00h
RO
8 bits
Reset RST/
Attr
Value PWR
RO 00h Uncore
Processor Configuration Registers
Description
Cache Line Size (CLS)
Implemented by PCI Express devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI
Express device functionality.
Description
Header Type Register (HDR)
Device 1 returns 81h to indicate that this is a multi function device
with bridge header layout.
Device 6 returns 01h to indicate that this is a single function device
with bridge header layout.
Description
Primary Bus Number (BUSN)
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since the
processor root port is an internal device and its primary bus is
always 0, these bits are read only and are hardwired to 0.
Datasheet, Volume 2