Cl1-Cache Line Size (D1:F0); Hdr1-Header Type (D1:F0); Pbusn1-Primary Bus Number (D1:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
8.1.7 CL1—Cache Line Size (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
7:0
8.1.8 HDR1—Header Type (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
7:0
8.1.9 PBUSN1—Primary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI bus 0.
Bit
7:0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
R/W Cache Line Size (Scratch pad): This field is implemented by PCI Express*
00h devices as a read/write field for legacy compatibility purposes but have no impact
on any PCI Express device functionality.
Access &
Default
RO Header Type Register (HDR): This field returns 01h to indicate that this is a
01h single function device with bridge header layout.
Access &
Default
RO Primary Bus Number (BUSN): Configuration software typically programs this
00h field with the number of the bus on the primary side of the bridge. Since device 1
is an internal device and its primary bus is always 0, these bits are read only and
are hardwired to 0.
Host-PCI Express* Graphics Bridge Registers (D1:F0)
1
0Ch
00h
R/W
8 bits
Description
1
0Eh
01h
RO
8 bits
Description
1
18h
00h
RO
8 bits
Description
117