Pci Revision Id Register; Pci Class Code Register; Pci Cache Line Size Register - Intel GD82559ER Datasheet

GD82559ER — Networking Silicon
Bits
24 Parity Error Detected
23 Fast Back-to-Back
20 Capabilities List
19:16 Reserved
7.1.4

PCI Revision ID Register

The Revision ID is an 8-bit read only register with a default value of 08h for the 82559ER. The
three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in
the EEPROM
7.1.5

PCI Class Code Register

The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, specific register level programming interface. The register is broken into three byte
size fields. The upper byte is a base class code and specifies the 82559ER as a network controller,
2H. The middle byte is a subclass code and specifies the 82559ER as an Ethernet controller, 0H.
The lower byte identifies a specific register level programming interface and the 82559ER always
returns a 0h in this field.
7.1.6

PCI Cache Line Size Register

In order for the 82559ER to support the Memory Write and Invalidate (MWI) command, the
82559ER must also support the Cache Line Size (CLS) register in PCI Configuration space. The
register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is
written to the register is ignored and the 82559ER does not use the MWI command. If a value other
than 8 or 16 is written into the CLS register, the 82559ER returns all zeroes when the CLS register
is read. The figure below illustrates the format of this register.
50
Table 6. PCI Status Register Bits
Name
This bit indicates whether a parity error has been detected. This bit is set to
1b when the following three conditions are met:
1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as the bus master for the operation in
which the error occurred.
3. The Parity Error Response bit in the command register (bit 6) is set.
In the 82559ER, the initial value of the Parity Error Detected bit is 0b. This
bit is set until cleared by writing a 1b.
This bit indicates a device's ability to accept fast back-to-back transactions
when the transactions are not to the same agent. A value of 0b disables
fast back-to-back ability. A value of 1b enables fast back-to-back ability. In
the 82559ER, this bit is read only and is set to 1b.
This bit indicates whether the 82559ER implements a list of new
capabilities such as PCI Power Management. A value of 0b means that this
function does not implement the Capabilities List. If this bit is set to 1b, the
Cap_Ptr register provides an offset into the 82559ER PCI Configuration
space pointing to the location of the first item in the Capabilities List. This
bit is set only if the power management bit in the EEPROM is set.
These bits are reserved and should be set to 0000b.
(Section 4.4, "Serial EEPROM Interface" on page
7 6 5
0 0 0
Figure 20. Cache Line Size Register
Description
28).
4 3 2
RW RW 0
1 0
0 0
Datasheet