Motorola DSP56800 Manual page 245

Instruction SZ
REP —
RND *
ROL —
ROR —
RTI
RTS —
SBC —
STOP —
SUB *
SWI —
Tcc —
TFR —
TST *
TSTW *
WAIT —
1. V is set if the MSB of the destination operand (bit 35 for an accumulator or bit 31 for the Y
register) is changed as a result of the left shift; V is cleared otherwise.
2. C is set if the MSB of the source operand (bit 35 for an accumulator or bit 31 for the Y
register) is set and is cleared otherwise.
3. C is set if bit 0 of the source operand is set and is cleared otherwise.
4. C is set if all bits specified by the mask are set and is cleared otherwise. Bits that are not set
in the mask should be ignored. If a bit-field instruction is performed on the status register,
all bits in this register selected by the bit field's mask can be affected.
5. C is set if all bits specified by the mask are cleared and is cleared otherwise. Ignore bits that
are not set in the mask. Note that if a bit-field instruction is performed on the status register,
all bits in this register selected by the bit field's mask can be affected.
6. C is set if the MSB of the result is cleared (bit 35 for an accumulator or bit 31 for the Y
register). The C bit is cleared if the MSB of the result is set.
7. For the accumulators, C is set if bit 31 of the source operand is set and is cleared otherwise.
For the Y1, Y0, and X0 registers, C is set if bit 15 of the source operand is set and is cleared
otherwise.
8. For the accumulators, C is set if bit 16 of the source operand is set and is cleared otherwise.
For the Y1, Y0, and X0 registers, C is set if bit 0 of the source operand is set and is cleared
otherwise.
Table A-9. Condition Code Summary (Continued)
L E U
T — —
CT *36 *36
— — —
— — —
Restored — (9)
— — —
C *36 *36
— — —
CT *A *A
— — —
— — —
T — —
CT *36 *36
— — —
— — —
NOTES:
Instruction Set Details
N Z V C
— — — —
*36 *36 *36 —
*16 *16 =0 (7)
*16 *16 =0 (8)
— — — —
*36 *36 *36 *36
— — — —
*A *A *A *A
— — — —
— — — —
— — — —
*36 *36 0 0
*36 *36 0 0
— — — —
Comments
Affects I1, I0 bits in SR
Never overflows
Never overflows
A-15