Two's-Complement Rounding; Figure 3-15 Convergent Rounding - Motorola DSP56800 Manual

16-bit digital signal processor
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Case I
: If A0 < $8000 (1/2), then round down (add nothing)
Before Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 0 0 1 1 X X X . . . . X X X
35
32 31
Case II
: If A0 > $8000 (1/2), then round up (Add 1 To A1)
Before Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 0 1 1 1 0 X X . . . . X X X
35
32 31
Case III
: If A0 = $8000 (1/2), and the LSB of A1 = 0 (even),then round down (add nothing)
Before Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 0 1 0 0 0 . . . . . . . . 0 0 0
35
32 31
Case IV
: If A0 = $8000 (1/2), and the LSB = 1 (odd), then round up (add 1 To A1)
Before Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 1 1 0 0 0 . . . . . . . . 0 0 0
35
32 31
*A0 is always clear; performed during RND, MPYR, and MACR
3.5.2

Two's-Complement Rounding

When this type of rounding is selected by setting the rounding bit in the OMR, one is added to the bit to the
right of the rounding point (bit 15 of A0) before the bit truncation during a rounding operation. Figure 3-16
shows the two possible cases.
0
A0
16 15
0
1
A0
16 15
0
0
A0
16 15
0
1
A0
16 15
0
Figure 3-15. Convergent Rounding
Data Arithmetic Logic Unit
After Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 0 0 0 0 . . . . . . . . . 0 0 0
35
32 31
After Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 1 0 0 0 . . . . . . . . . 0 0 0
35
32 31
After Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 0 0 0 0 0 . . . . . . . . . 0 0 0
35
32 31
After Rounding
A2
A1
X X . . X X X X X . . . X X X 0 1 1 0 0 0 0 . . . . . . . . . 0 0 0
35
32 31
Rounding
A0*
16 15
0
A0*
16 15
0
A0*
16 15
0
A0*
16 15
0
AA0048
3-31

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