Index By Offset N: (Rn+N), (Sp+N); Figure 4-7 Address Register Indirect: Indexed By Offset N - Motorola DSP56800 Manual

16-bit digital signal processor
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Address Generation Unit
4.2.2.5

Index by Offset N: (Rn+N), (SP+N)

The address of the operand is the sum of the contents of the address register Rn or SP and the contents of
the address offset register N. This addition occurs before the operand can be accessed and, therefore,
inserts an extra instruction cycle. The content of N is treated as a two's-complement signed number. The
contents of the Rn and N registers are unchanged by this addressing mode. The type of arithmetic (linear or
modulo) used to add N to Rn is determined by M01 for R0 and R1 and is always linear for R2, R3, and SP.
This reference is classified as a memory reference. See Figure 4-7.
Before Execution
A2
A1
A
F
E
D
35 32 31
15
$7003
X
$7000
X
R0
15
N
15
M01
15
Assembler syntax: X:(Rn+N), X:(SP+N)
Additional instruction execution cycles: 1
Additional effective address program words: 0
Figure 4-7. Address Register Indirect: Indexed by Offset N
4-14
Indexed by Offset N Example
A0
C
B
A
9
8
7
16 15
0
X Memory
0
X
X
X
X
X
X
$7000
0
+
$0003
0
$FFFF
0
DSP56800 Family Manual
: MOVE A1,X:(R0+N)
After Execution
A2
A1
A
F
E
D
C
B
35 32 31
16 15
X Memory
15
$7003
E
D
C
$7000
X
X
X
R0
$7000
15
N
$0003
15
M01
$FFFF
15
A0
A
9
8
7
0
0
B
X
0
0
0
AA0020

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