A.5 Instruction Timing - Motorola DSP56800 Manual

9. The "?" bit is set according to value pulled from stack.
10. If the SR is specified as a destination operand (for example,
is set according to the corresponding bit of the source operand. If SR is not specified as a
destination operand, none of the status bits are affected.
11. C is set if bit 0 of the SP register is set and is cleared otherwise.
12. N is set if bit 15 of the HWS register is set before the ENDDO and is cleared otherwise.
13. Z is set if bits 15–0 of the HWS register are zero before the ENDDO and is cleared
otherwise.
14. The lowest eight condition code bits in the status register are loaded with the value in the
8-bit FISR register.
15. The V bit for the IMPY instruction is set if the calculated integer product does not fit in 16
bits.
16. The setting of the N bit for the ASRAC and LSRAC instructions depends on the OMR's
SA bit. If SA is one, then the N bit is equal to bit 31 of the result. If SA is zero, then N is
equal to bit 35 of the result.
17. When SA is zero and CC is zero for the IMPY instruction, the N bit is set using *16. When
SA is one or CC is set to one, this bit is set as described in Section A.4.1.5, "Negative
(N)—Bit 3."
18. When CC is one for the ASLL instruction, the N bit is cleared. When CC is zero, this bit is
set as described under Section A.4.1.5, "Negative (N)—Bit 3."
See Section 3.6, "Condition Code Generation," on page 3-33 for additional information on condition
codes.
A.5 Instruction Timing
This section describes how to calculate the DSP56800 instruction timing manually using the provided
tables. Three complete examples are presented to illustrate the use of the tables. Alternatively, the user can
obtain the number of instruction program words and the number of oscillator clock cycles required for a
given instruction by using the simulator; this is a simple and fast method of determining instruction timing
information.
The number of words for an instruction depends on the instruction operation and its addressing mode. The
symbols used in one table may reference subsequent tables to complete the instruction word count.
The number of oscillator clock cycles per instruction is dependent on many factors, including the number
of words per instruction, the addressing mode, whether the instruction fetch pipe is full or not, the number
of external bus accesses, and the number of wait states inserted in each external access. The symbols used
in one table may reference subsequent tables to complete the execution clock-cycle count.
The tables in this section present the following information:
• Table A-11 on page A-18 gives the number of instruction program words and the number of
machine clock cycles for each instruction mnemonic.
• Table A-12 on page A-19 gives the number of additional instruction words (if any) and additional
clock cycles (if any) for each type of parallel move operation.
• Table A-13 on page A-20 gives the number of additional (if any) clock cycles for each type of
MOVEC operation.
A-16 DSP56800 Family Manual
), each bit
MOVE X:(R0),SR