Memory Locations Not Available For Modulo Buffers; Pipeline Dependencies - Motorola DSP56800 Manual

4.3.2.7.3

Memory Locations Not Available for Modulo Buffers

For cases where the size of a buffer is not a power of two, there will be a range of memory locations
immediately after the buffer that are not accessible with modulo addressing. Lower boundaries for modulo
buffers always begin on an address where the lowest k bits are zeros—that is, a power of two. This means
that for buffers that are not an exact power of two, there are locations above the upper boundary that are
not accessible through modulo addressing.
In Figure 4-16 on page 4-27, for example, the buffer size is 37, which is not a power of two. The smallest
power of two greater than 37 is 64. Thus, there are 64 - 37 = 27 memory locations which are not accessible
with modulo addressing. These 27 locations are between the upper boundary + 1 = $00A5 and the next
power of two boundary address - 1 = $00C0 - 1 = $00BF.
These locations are still accessible when no modulo arithmetic is performed. Using linear addressing (with
the R2 or R3 pointers), absolute addresses, or the no-update addressing mode makes these locations
available.
4.4

Pipeline Dependencies

There are some cases within the address generation unit where the pipelined nature of the DSP core can
affect the execution of a sequence of instructions. The pipeline dependencies are caused by a write to an
AGU register immediately followed by an instruction that uses that same register in an address arithmetic
calculation. When there is a dependency caused by a write to the N register, the DSP automatically stalls
the pipeline one cycle. If a dependency is caused by a write to the R0-R3, SP, or M01 registers, however,
there is no pipeline stall. This is also true if a bit-field operation is performed on the N register. Instead, the
user must take care to avoid this case by rearranging the instructions or by inserting a NOP instruction to
break the instruction sequence.
Several instruction sequences are presented in the following examples to examine cases where their
pipeline dependency occurs, how this affects the machine, and how to correctly program to avoid these
dependencies.
In Example 4-4 there is no pipeline dependency since the N register is not used in the second instruction.
Since there is no dependency, no extra instruction cycles are inserted.
Example 4-4. No Dependency with the Offset Register
MOVE #$7,N
MOVE X:(R2)+,X0
In Example 4-5 there is no pipeline dependency since the R2 and N registers, used in the address
calculation, are not written in the previous instruction. Since there is no dependency, no extra instruction
cycles are inserted.
Example 4-5. No Dependency with an Address Pointer Register
MOVE #$7,R1
MOVE X:(R2)+N,X0
In Example 4-6 there is no pipeline dependency since there is no address calculation performed in the
second instruction. Instead, the R1 register is used as the source operand in a MOVE instruction, for which
there is no pipeline dependency. Since there is no dependency, no extra instruction cycles are inserted.
; Write to the N register
; N not used in this instruction
; Write to R1 register
; R1 not used in this instruction
Address Generation Unit
Pipeline Dependencies
4-33