Table A-10 Instruction Timing Symbols - Motorola DSP56800 Manual

• Table A-14 on page A-20 gives the number of additional (if any) clock cycles for each type of
MOVEM operation.
• Table A-15 on page A-20 gives the number of additional (if any) clock cycles for each type of
bit-field manipulation (BFCHG, BFCLR, BFSET, BFTSTH, BFTSTL, BRCLR, and BRSET)
operation.
• Table A-16 on page A-20 gives the number of additional clock cycles (if any) for each type of
branch or jump (Bcc, Jcc, and JSR) operation.
• Table A-17 on page A-21 gives the number of additional clock cycles (if any) for the RTS or RTI
instruction.
• Table A-18 on page A-21 gives the number of additional clock cycles (if any) for the TSTW
instruction.
• Table A-19 on page A-21 gives the number of additional instruction words (if any) and additional
clock cycles (if any) for each effective addressing mode.
• Table A-20 on page A-22 gives the number of additional clock cycles (if any) for external data,
external program, and external I/O memory accesses.
The symbols used in the tables are summarized in Table A-10.
Symbol
aio
ap
ax
axx
ea
jx
mv
mvb
mvc
mvm
mvp
mvs
rx
wp
wx
The assumptions for calculating execution time are the following:
• All instruction cycles are counted in oscillator clock cycles. Two oscillator clock cycles are
equivalent to one instruction cycle.
Table A-10. Instruction Timing Symbols
Time required to access an I/O operand
Time required to access a P memory operand
Time required to access an X memory operand
Time required to access X memory operands for double read
Time or number of words required for an effective address
Time required to execute part of a jump-type instruction
Time or number of words required for a move-type operation
Time required to execute part of a bit-manipulation instruction
Time required to execute part of a MOVEC instruction
Time required to execute part of a MOVEM instruction
Time required to execute part of a MOVEP instruction
Time required to execute part of a MOVES instruction
Time required to execute part of an RTS instruction
Number of wait states used in accessing external P memory
Number of wait states used in accessing external X memory
Instruction Set Details
Description
A-17