A.4.2 Effects Of The Operating Mode Register's Sa Bit; A.4.3 Effects Of The Omr's Cc Bit - Motorola DSP56800 Manual

A.4.2 Effects of the Operating Mode Register's SA Bit
The SA bit in the Operating Mode Register (OMR) can affect the computation of certain condition code
bits. This bit enables the MAC Output Limiter within the data ALU. When enabled, the results of many
operations are limited to fit with 32 bits, the extension portion containing only sign information. This
limiting operation has both direct and indirect effects on the way condition codes are computed.
The SA bit directly affects the following condition code bits:
• U—cleared if saturation occurs in the MAC Output Limiter
• V—set when saturation occurs in the MAC Output Limiter
The remaining bits in the Condition Code Register are not affected by the SA bit, with the following
exceptions:
• L—may be indirectly affected through effects on the V bit
• N—affected only by the ASRAC, LSRAC, and IMPY instructions
• C—affected only by the ASL instruction
The value of the SA bit is designed not to affect condition code computation for the TSTW instructions.
Only the U condition code bit is affected by the SA bit for the CMP instruction. These instructions operate
independently of the CC bit and correctly generate both signed and unsigned condition codes.
The SA bit only affects operations in the data ALU, not operations performed in other blocks. These
include move instructions, bit-manipulation instructions, and address calculations performed by the AGU.
When SA is set to one for an application, condition codes are not always
set in an intuitive manner. It is best to examine the instruction details to
determine the effect on condition codes when SA is one. See Section A.7,
"Instruction Descriptions."
A.4.3 Effects of the OMR's CC Bit
The CC bit in the OMR may affect the computation of the condition code bits. The CC bit establishes how
many of the bits of an arithmetic or logic operation result are used when calculating condition codes.
Specifically:
• When CC = 0, the result is interpreted as 36 bits with a valid extension portion.
• When CC = 1, the result is interpreted as 32 bits with the extension portion ignored.
Signed values can be computed in both cases, but computation of unsigned values must be performed with
the CC bit set to one. Without setting CC to one prior to executing the TST and CMP instructions, the HI,
HS, LO, and LS branch/jump conditions cannot be used.
When the CC bit is set, the following condition code bits are affected:
• V—set based on the MSB of the result's MSP portion
• Z—set using only the MSP and LSP portions of the result
The remaining bits in the Condition Code Register are not affected by the CC bit, with the following
exceptions:
• L—may be indirectly affected through effects on the V bit
• N—affected only by the ASRAC, LSRAC, IMPY, and ASLL instructions
• C—affected only by the ASL instruction
NOTE:
Instruction Set Details A-11