Figure 7-12 Stop Instruction Sequence Recovering With Reset - Motorola DSP56800 Manual

5. The exact elapsed time for clock recovery is unpredictable. The external device that asserts
IRQA must wait for some positive feedback, such as specific memory access or a change
in some predetermined I/O pin, before deasserting IRQA.
The STOP sequence totals 131,104 T cycles (if the SD equals 0) or 48 T cycles (if the SD equals 1) in
addition to the period with no clocks from the stop fetch to the IRQA vector fetch (or next instruction).
However, there is an additional delay if the internal oscillator is used. An indeterminate period of time is
needed for the oscillator to begin oscillating and then stabilize its amplitude. The processor will still count
131,072 T cycles (or 16 T cycles), but the period of the first oscillator cycles will be irregular; thus, an
additional period of 19,000 T cycles should be allowed for oscillator irregularity (the specification
recommends a total minimum period of 150,000 T cycles for oscillator stabilization). If an external
oscillator is used that is already stabilized, no additional time is needed.
The PLL may or may not be disabled when the chip enters the stop state. If it is disabled and will not be
re-enabled when the chip leaves the stop state, the number of T cycles will be much greater because the
PLL must regain lock.
If the STOP instruction is executed when the IRQA signal is asserted, the clock generator will not be
stopped, but the four-phase clock will be disabled for the duration of the 128K T cycle (or 16 T cycle)
delay count. In this case the STOP instruction looks like a 131,072 T + 35 T cycle (or 51 T cycle) NOP,
since the STOP instruction itself is eight instruction cycles long (32 T) and synchronization of IRQA is 3
T, totaling 35 T.
A stack error interrupt that is pending before the processor enters the stop state is not cleared and will
remain pending. During the clock-stabilization delay in stop mode, any edge-triggered IRQ interrupts are
cleared and ignored.
If RESET is used to restart the processor (see Figure 7-12), the 128K T cycle delay counter would not be
used, all pending interrupts would be discarded, and the processor would immediately enter the reset
processing state as described in Section 7.1, "Reset Processing State." For example, the stabilization time
recommended in DSP56824 Technical Data for the clock (RESET should be asserted for this time) is only
50 T for a stabilized external clock, but is the same 150,000 T for the internal oscillator. These stabilization
times are recommended and are not imposed by internal timers or time delays. The DSP fetches
instructions immediately after exiting reset. If the user wishes to use the 128K T (or 16 T) delay counter, it
can be started by asserting IRQA for a short time (about two clock cycles).
RESET
Interrupt Control Cycle 1
Interrupt Control Cycle 2
Fetch
Decode
Execute
Stop Cycle Count
RESET = Interrupt
n = Normal Instruction Word
nA, nB, nC = Instructions in Reset Routine
STOP = Interrupt Instruction Word
Figure 7-12. STOP Instruction Sequence Recovering with RESET
Processor Enters
Reset State
n3 n4 — —
n2 STOP — —
n1 n2 STOP —
1 2 3 4
Interrupts and the Processing States
Stop Processing State
Processor Leaves Reset State
nop nA nB
nop nop nA
nop nop nop
Clock Stopped
nC nD nE
nB nC nD
nA nB nC
AA0078
7-21