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Motorola 68HC12 User Manual

Motorola 68HC12 User Manual



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Summary of Contents for Motorola 68HC12

  • Page 1: Table Of Contents

    Electrical and Computer Systems Engineering Rensselaer Polytechnic Institute Revision 1.1 8/10/00 Table of Contents: page 1. Introduction 2. Basic Programming notes for the 68HC12 3. D-Bug 12 Monitor Program 4. 68HC12 Hardware a) Ports b) A/D Converter c) Timer Functions i) Timer Output Compare...
  • Page 2: Introduction

    Also added is a second SCI connector and a new interrupt, called a Key Wakeup interrupt. This manual is intended to provide a brief introduction to the 68HC12 and how to program it in C using the Introl C compiler 4.00.
  • Page 3: Basic Programming Notes For The 68Hc12

    2. Basic Programming Notes: There are 3 header files that must be included with any code written for the 68HC12 using the Introl C compiler. These are: HC812A4.H - This file contains all the register declarations for the 6812. INTROL.H - This file contains several function declarations needed by Introl to compile the program.
  • Page 4: D-Bug 12 Monitor Program

    D-Bug12 Functions Readers interested in a more in-depth explanation of the D-Bug12 routines are referred to Motorola Document an1280a, "Using the Callable Routines in D-Bug 12" (available on the web at getchar This function will get a single character of input from the user.
  • Page 5 DB12->printf("This is the value of num: %d", num); d, i int, signed decimal number int, unsigned octal number int, unsigned hexadecimal number using a-f for 10-15 int, unsigned hexadecimal number using A-F for 10-15 int, unsigned decimal int, single character char *, display from a string until '\0' void *, pointer putchar...
  • Page 6 toupper This routine is used to convert lower case letters to upper case letters. Function Prototype: int toupper(int c); Return Value: The uppercase value of c. If c is already an uppercase letter it returns c. isalpha This routine determines if c is a member of the set a…z and A…Z Function Prototype: int isalpha(int c);...
  • Page 7: 4. 68Hc12 Hardware

    All port names are of the format _H12PORTx, where x is the capital letter of the port you are trying to access. i.e. Port A is _H12PORTA. Ports A and B are used as the address bus for the 68HC12. They are not usable as I/O by the programmer.
  • Page 8: B) A/D Converter

    A to D Converter: This section covers the basic function of the A/D converter. The A/D converter uses a dedicated port, port AD, for its inputs. There are 8 A/D converter channels on the HC12 and, unlike the 6811, there are also 8 A/D registers allowing 8 simultaneous readings.
  • Page 9 Table 2: Prescalar Values Prescale Value Divisor___ 00000 Do not use 00001 00010 00011 00100 00101 00110 00111 01xxx Do not use 1xxxx Do not use _H12ADTCTL5 is used to select the conversion mode, which channels are to be converted and to initiate the conversions. The conversion sequence is started by any write made to this register.
  • Page 10 0* 1* ADR3 1* 0* ADR4 1* 0* ADR5 1* 1* ADR6 1* 1* ADR7 0* 0* Reserved ADR0 0* 0* Reserved ADR1 0* 1* Reserved ADR2 0* 1* Reserved ADR3 1* 0* V RH ADR4 1* 0* V RL ADR5 1* 1* (V RH + V RL )/2...
  • Page 11 DB12->out2hex(_H12ADR1H); DB12->printf("\n\r"); DB12->out2hex(_H12ADR2H); DB12->printf("\n\r"); DB12->out2hex(_H12ADR3H);...
  • Page 12: C) Timer Functions

    For output compare operations the value in the register is used to trigger an action. The 68HC12 also allows the user to assign pull-up resistors to the timer module inputs. This is done by writing a one to TPE in _H12TMSK2.
  • Page 13: I) Timer Output Compare

    Timer Output Compare The output compare on the 68HC12 is very similar to that of the 68HC11. The user selects an action to occur when the output compare is triggered and the time at which the action occurs. The processor will then carry out this action accordingly.
  • Page 14 Output Compare 7 Output Compare 7 has a special feature that makes it very powerful. Output Compare 7 allows the programmer to change the state of any of the output compare pin, without changing the operation that is performed by that Output Compare.
  • Page 15: Iii) Timer Compare Force Register

    Timer Compare Force Register This is a special register that allows the programmer to cause an output compare to trigger. Writing to bit n in this register causes the action which is programmed for output compare n to occur immediately. This is the same as if a successful comparison had just taken place with the TCn register.
  • Page 16: Interrupt Service Routines

    5. Interrupt Service Routines Overview: Overview: The 68HC12 provides a wide array of interrupts that can be used by the programmer. Some of these are similar to interrupts found on the 68HC11, such as the RTI and timer overflow. Others are new to the 68HC12 such as the key wakeups and A/D converter interrupts.
  • Page 17: B) Interrupt Priority

    Interrupt Priority: Interrupts on the 68HC12 do not all occur simultaneously. Rather there is a hierarchy of priority for the interrupts. The default priority order is: Reset COP Clock Monitor Fail Reset COP Failure Reset Trap XIRQ Timer0 10) Timer1...
  • Page 18: C) Real Time Interrupt

    Interrupt Service Routines example code and explanations This section includes explanations of all the different interrupts and sample code of the function. Real Time Interrupt: Operation The operation of the RTI is controlled by _H12RTICTL. Bit 7 is the Real Time Interrupt Enable (RTIE).
  • Page 19: D) Timer Overflow Interrupt

    Timer Overflow Interrupt: Operation The Timer Overflow Interrupt (TOI) functions by generating an interrupt every time the "free running" counter overflows. The free running counter is a 16 bit value and is constantly running in the background when the timer is enabled. The TOI is set up in the _H12TMSK2 register by writing a one to Timer Overflow Interrupt Enable (TOIE).
  • Page 20: E) Pulse Accumulator Edge Triggered Interrupt

    Pulse Accumulator Edge Triggered Interrupt: Operation This section describes how to set up the Pulse Accumulator for edge triggered operation. The Pulse Accumulator is enabled by setting the Pulse Accumulator Enable (PAEN) in _H12PACTL to one. There are two other control bits in _H12PACTL, PAMOD and PEDGE.
  • Page 21 _H12PAFLG: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused unused unused unused unused unused PAOVIF PAIF The value of the pulse accumulator is stored in _H12PACNT. Sample Code This code detects the edge and triggers an interrupt. _ _mod2_ _ void PAEdgeInt();...
  • Page 22: F) Pulse Accumulator Overflow Triggered Interrupt

    Pulse Accumulator Overflow Triggered Interrupt: Operation This operation triggers an interrupt every time the pulse accumulator overflows. Whenever the pulse accumulator overflows from 0xFFFF to 0x0000, the ISR will trigger. The set up of this interrupt is very similar to the edge triggered interrupt, although PAMOD and PAEDGE have no effect on the interrupt.
  • Page 23: G) Output Compare Interrupt

    Output Compare Interrupt: Operation The output compare interrupt calls an ISR every time a successful output compare is detected. The output compare is setup like the non- interrupt based output compare, with the major difference being that the action which is to occur on a successful compare does not need to be specified.
  • Page 24: H) Input Capture Interrupt

    Input Capture Interrupt: Operation Like the output compare interrupt, the input capture interrupt is very similar to the non-interrupt based input capture. The _H12TIOS and _H12TCTL3 and _H12TCTL4 are set up the same as for the non-interrupt input capture. The difference is that _H12TMSK1 is used to determine which channel(s) will be used to generate an interrupt(s).
  • Page 25: I) A/D Converter Interrupt

    A to D Converter Interrupt: Operation This is similar to the non-interrupt based A/D converter. However instead of having to poll the flag to determine when the A/D cycle has been completed, an interrupt is generated when the conversion is completed. In order to make use of the A/D interrupt the ASCIE bit in _H12ADTCTL2 must be set to 1.
  • Page 26: J) Irq Interrupt

    When it is 1 the IRQ will be falling edge triggered. The IRQ is automatically cleared by the hardware in the 68HC12. There are a few differences between the IRQ on the HC11 and the HC12. Unlike the HC11, the IRQ is not time protected.
  • Page 27: K) Port H Key Wakeup Interrupt

    Port H Key Wakeup Interrupt: Operation This is a new feature that was incorporated into the HC12. This generates an interrupt when the appropriate edge is detected on the input to the port. This is ideal for use with a keypad, or can be used as extra IRQ lines for the HC12. Each bit of Port H can be used to generate a Key Wakeup interrupt when a falling edge is detected.
  • Page 28: L) Port J Key Wakeup Interrupt

    Port J Key Wakeup Interrupt: Operation The Port J key Wakeup Interrupt is a more powerful version of the Port H Key Wakeup Interrupt. Unlike the Port H Key Wakeup, Port J can be set to trigger on either a rising edge or a falling edge input.
  • Page 29 void _ _main(void) DB12->SetUserVector(PortJKey, KeyJ); // assign the vector address _H12KPOLJ=0x00; // falling edge sets flag _H12KWIFJ=0xFF; // clear any flags that may be set _H12PUPSJ=0xFF; // pull up _H12PULEJ=0xFF; // pull up enabled all bits _H12KWIEJ=0xFF; // Enable all bits of J for keypad while(1) // Infinite loop _ _mod2_ _ void KeyJ(void)
  • Page 30 = push button connection between grid wires Pins normally pulled high (through pull-up resistors in 6812) - switch closure will temporally pull bit low Pins normally grounded (held low) Keypad wiring diagram - The keypad is a passive device with only switches that connect wires on the crosspoint matrix of 4 x 4 wires.

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