Lsrac - Motorola DSP56800 Manual

LSRAC

Operation:
S1 >> S2 + D → D
(no parallel move)
Description: Logically shift the first 16-bit source operand (S1) to the right by the value contained in the lowest 4
bits of the second source operand (S2), and accumulate the result with the value in the destination reg-
ister (D).
Usage:
This instruction is used for multi-precision logical right shifts.
Example:
LSRAC
Before Execution
0 0000
A2 A1
Explanation of Example:
Prior to execution, the Y1 register contains the value to be shifted ($C003), the X0 register contains
the amount by which to shift ($0004), and the destination accumulator contains $0:000:0099. The
LSRAC instruction logically shifts the value $C003 four bits to the right and accumulates this result
with the value already in the destination register A. Since the destination is an accumulator, the exten-
sion word (A2) is filled with sign extension.
Condition Codes Affected:
15 14
LF *
See Section 3.6.2, "36-Bit Destinations—CC Bit Set," on page 3-34 and Section 3.6.4, "20-Bit Desti-
nations—CC Bit Set," on page 3-34 for the case when the CC bit is set.
Logical Right Shift with Accumulate
Y1,X0,A
0099
A0
Y1
C003
X0
0004
MR
13 12 11 10 9
* * * * I1
N — Set if bit 35 of A or B result is set except during saturation
Z — Set if A or B result equals zero
Instruction Set Details
Assembler Syntax:
LSRAC S1,S2,D
; 16-bit add
After Execution
0 0C00
A2 A1
CCR
8 7 6 5 4
I0 SZ L E U
LSRAC
(no parallel move)
3099
A0
Y1
C003
X0
0004
3 2 1 0
N Z
V C
A-99