Figure A-2 Status Register (Sr; A.4.1 The Condition Code Bits; A.4.1.1 Size (Sz)—Bit 7 - Motorola DSP56800 Manual

A.4.1 The Condition Code Bits
The DSP56800 family defines eight condition code bits, which are contained in the lower-order 8 bits of
the Status Register (SR) as follows:
SR
Status Register
Reset = $0300
Read/Write
* Indicates reserved bits, read as zero and should be written with zero for future compatibility
The C, V, Z, N, U, and E bits are true condition code bits that reflect the condition of the result of a data
ALU operation. These condition code bits are not affected by address ALU calculations or by data
transfers over the CGDB. The N, Z, and V condition code bits are updated by the TSTW instruction, which
can operate on both memory and registers. The L bit is a latching overflow bit that indicates that an
overflow has occurred in the data ALU or that limiting has occurred when moving an accumulator register
to memory. The SZ bit is a latching bit that indicates the size of an accumulator when it is moved to data
memory.
A.4.1.1 Size (SZ)—Bit 7
The SZ bit is set only when moving one of the two accumulators (A or B) to data memory. It is set if,
during this move, bits 30 and 29 of the specified accumulator are not the same—that is, not 00 or 11—as
follows:
SZ = SZ | (Bit 30 ⊕ Bit 29)
SZ is not affected otherwise. Note that the SZ bit is latched once it is set—it is only cleared by a processor
reset or an instruction that explicitly clears it.
SZ is not affected by the OMR's CC or SA bits.
MR
15 14 13 12 11
LF
* * * *
LF—Loop Flag
I1,I0—Interrupt Mask
SZ—Size
L—Limit
E—Extension
U—Unnormalized
N—Negative
Z—Zero
V—Overflow
C—Carry
Figure A-2. Status Register (SR)
Instruction Set Details
10 9 8 7 6
I1 I0 L
SZ
*
CCR
5 4 3 2 1
E U N Z V
0
C
A-7