Table 6-28 Agu Arithmetic Instructions; Table 6-29 Bit-Manipulation Instructions - Motorola DSP56800 Manual

Operation
LEA
TSTW
Operation
BFTSTH
BFTSTL
Table 6-28. AGU Arithmetic Instructions
Operands C W
(Rn)+ 2
(Rn)- 2
(Rn)+N 2
(R2+xx) 2
(SP-xx) 2
(Rn+xxxx) 4
(Rn)- 2
Table 6-29. Bit-Manipulation Instructions
Operands
#xxxx,DDDDD
#xxxx,X:(R2+xx)
#xxxx,X:(SP-xx)
#xxxx,X:aa
#xxxx,X:pp
#xxxx,X:xxxx
#xxxx,DDDDD
#xxxx,X:(R2+xx)
#xxxx,X:(SP-xx)
#xxxx,X:aa
#xxxx,X:pp
#xxxx,X:xxxx
Instruction Set Introduction
DSP56800 Instruction Set Summary
1 Increment the Rn pointer register
1 Decrement the Rn pointer register
1 Add N index register to the Rn register and store the
result in the Rn register
1 Add a 6-bit unsigned immediate value to R2 and store
in the R2 pointer
1 Subtract a 6-bit unsigned immediate value from SP and
store in the SP register
2 Add a 16-bit signed immediate value to the specified
source register
1 Test and decrement AGU register. Refer to Table 6-24
for other forms of TSTW that are executed in the Data
ALU.
C W
4 2 BFTSTH tests all bits selected by the 16-bit
immediate mask. If all selected bits are set,
6 2
then the C bit is set. Otherwise it is cleared.
6 2
All registers in DDDDD are permitted except
HWS.
4 2
X:aa represents a 6-bit absolute address.
Refer to Absolute Short Address (Direct
4 2
Addressing): <aa> on page 4-22
X:pp represents a 6-bit absolute I/O address.
6 3
4 2 BFTSTL tests all bits selected by the 16-bit
immediate mask. If all selected bits are clear,
6 2
then the C bit is set. Otherwise it is cleared.
6 2
All registers in DDDDD are permitted except
HWS.
4 2
X:aa represents a 6-bit absolute address.
Refer to Absolute Short Address (Direct
4 2
Addressing): <aa> on page 4-22
X:pp represents a 6-bit absolute I/O address.
6 3
Comments
Comments
6-25