Overview And Architecture - Motorola DSP56800 Manual

Data Arithmetic Logic Unit
• Division iteration
• Normalization iteration
• Conditional register moves (Tcc)
• Saturation (limiting)
3.1

Overview and Architecture

The major components of the data ALU are the following:
• Three 16-bit input registers (X0, Y0, and Y1)
• Two 32-bit accumulator registers (A and B)
• Two 4-bit accumulator extension registers (A2 and B2)
• An accumulator shifter (AS)
• One data limiter
• One 16-bit barrel shifter
• One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit
A block diagram of the data ALU unit is shown in Figure 3-1 on page 3-3, and its corresponding
programming model is shown in Figure 3-2 on page 3-4. In the programming model, accumulator "A"
refers to the entire 36-bit accumulator register, whereas "A2," "A1," and "A0" refer to the directly
accessible extension, most significant portions, and least significant portions of the 36-bit accumulator,
respectively. Instructions can access the register as a whole or by these individual portions (see
Section 3.1.2, "Data ALU Accumulator Registers," on page 3-4 and Section 3.2, "Accessing the
Accumulator Registers," on page 3-7). The blocks and registers within the data ALU are explained in the
following sections.
3-2 DSP56800 Family Manual