Motorola DSP56800 Manual page 333

MAC
Operation:
D + S1 * S2 → D (no parallel move)
D + S1 * S2 → D (one parallel move)
D + S1 * S2 → D (two parallel reads)
Description: Multiply the two signed 16-bit source operands (S1 and S2) and add or subtract the product to or from
the specified 36-bit destination accumulator (D). The "-" sign option is used to negate the specified
product prior to accumulation. This option is not available when a single parallel move is performed
or when two parallel read operations are performed.
Usage:
This instruction is used for multiplication and accumulation of fractional data or integer data when a
full 32-bit product is required (see Section 3.3.5.2, "Integer Multiplication," on page 3-20). When the
destination is a 16-bit register, this instruction is useful only for fractional data.
Example:
MAC
Before Execution
0 0003
A2 A1
Explanation of Example:
Prior to execution, the 16-bit X0 register contains the value $4000, the 16-bit Y1 register contains the
value $0AA0, and the 36-bit A accumulator contains the value $0:0003:0003. Execution of the
MAC X0,Y1,A instruction multiplies the 16-bit signed value in the X0 register by the 16-bit signed
value in Y1, adds the resulting 32-bit product to the 36-bit A accumulator, and stores the result
($0:0553:0003) into the A accumulator. In parallel, X0 and Y1 are updated with new values fetched
from data memory, and the two address registers (R1 and R3) are post-incremented by one.
Condition Codes Affected:
15 14
LF *
See Section 3.6.5, "16-Bit Destinations," on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, "36-Bit Destinations—CC Bit Set," on page 3-34 and Section 3.6.4, "20-Bit Desti-
nations—CC Bit Set," on page 3-34 for the case when the CC bit is set.
Multiply-Accumulate
X0,Y1,A
0003
A0
X0
4000
Y1
0AA0
MR
13 12 11 10 9
* * * * I1
SZ — Set according to the standard definition of the SZ bit (parallel move)
L — Set if limiting (parallel move) or overflow has occurred in result
E — Set if the signed integer portion of A or B result is in use
U — Set according to the standard definition of the U bit
N — Set if bit 35 of A or B result is set except during saturation
Z — Set if A or B result equals zero
V — Set if overflow has occurred in A or B result
Instruction Set Details
Assembler Syntax:
MAC (+)S1,S2,D
MAC S1,S2,D
MAC S1,S2,D
X:(R1)+,Y1 X:(R3)+,X0
After Execution
0 0553
A2 A1
CCR
8 7 6 5 4
SZ L E U
I0
MAC
(no parallel move)
(one parallel move)
(two parallel reads)
0003
A0
X0
4000
Y1
0AA0
3 2 1 0
N Z V
C
A-103