Figure 6-4 Pipelining; Memory Access Processing - Motorola DSP56800 Manual

Fetch
Decode
Execute
Instruction Cycle
Each instruction requires a minimum of three instruction cycles (six machine cycles) to be fetched,
decoded, and executed. A new instruction may be started after two machine cycles, making the throughput
rate to be one instruction executed every instruction cycle for single-cycle instructions. Two-word
instructions require a minimum of eight machine cycles to execute, and a new instruction may start after
four machine cycles.
6.7.2

Memory Access Processing

One or more of the DSP memory sources (X data memory and program memory) may be accessed during
the execution of an instruction. Three address buses (XAB1, XAB2, and PAB) and three data buses
(CGDB, XDB2, and PDB) are available for internal memory accesses during one instruction cycle, but
only one address bus and one data bus are available for external memory accesses (when the external bus is
available). If all memory sources are internal to the DSP, one or more of the two memory sources may be
accessed in one instruction cycle (that is, program memory access, or program memory access plus an X
memory reference, or program memory access with two X memory references).
For instructions that contain two X memory references, the second transfer
using XAB2 and XDB2 may not access external memory. All accesses
across these buses must access internal memory only.
See Section 7.2.2, "Instruction Pipeline with Off-Chip Memory Accesses," on page 7-3 for a discussion of
off-chip memory accesses.
F1 F2 F3 F3e
D1 D2 D3
E1 E2
1 2 3 4
Figure 6-4. Pipelining
NOTE:
Instruction Set Introduction
The Instruction Pipeline
F4 F5 F6 ...
D3e D4 D5 ...
E3 E3e E4 ...
5 6 7 ...
6-31