Motorola DSP56800 Manual

16-bit digital signal processor.
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DSP56800
16-Bit Digital Signal Processor
Family Manual
DSP56800FM/D
Rev. 2.0, 05/2002

   Related Manuals for Motorola DSP56800

   Summary of Contents for Motorola DSP56800

  • Page 1

    DSP56800 16-Bit Digital Signal Processor Family Manual DSP56800FM/D Rev. 2.0, 05/2002...

  • Page 2

    Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

  • Page 3: Table Of Contents

    Phase Lock Loop (PLL) ......... . 2-8 DSP56800 Core Programming Model ........2-8...

  • Page 4: Table Of Contents

    Unsigned Arithmetic..........3-36 DSP56800 Family Manual...

  • Page 5: Table Of Contents

    Chapter 4 Address Generation Unit Architecture and Programming Model ........4-2 4.1.1 Address Registers (R0-R3) .

  • Page 6: Table Of Contents

    Move Instructions ..........6-9 DSP56800 Family Manual...

  • Page 7: Table Of Contents

    POP Alias ........... . 6-14 DSP56800 Instruction Set Summary ........6-14 6.6.1...

  • Page 8: Table Of Contents

    Interrupts ............8-30 viii DSP56800 Family Manual...

  • Page 9: Table Of Contents

    8.10.1 Setting Interrupt Priorities in Software ......8-30 8.10.1.1 High Priority or a Small Number of Instructions ....8-31 8.10.1.2 Many Instructions of Equal Priority .

  • Page 10: Table Of Contents

    Autocorrelation Algorithm ........B-24 DSP56800 Family Manual...

  • Page 11: Table Of Contents

    List of Tables Table 3-1 Accessing the Accumulator Registers ....... . 3-7 Table 3-2 Interpretation of 16-Bit Data Values .

  • Page 12: Table Of Contents

    Additional Cycles for Off-Chip Memory Accesses ..... . 7-4 Table 7-4 DSP56800 Core Reset and Interrupt Vector Table..... . . 7-7 Table 7-5 Interrupt Priority Level Summary.

  • Page 13: Table Of Contents

    Table A-12 Parallel Move Timing..........A-19 Table A-13 MOVEC Timing Summary .

  • Page 14

    DSP56800 Family Manual...

  • Page 15

    DSP56800 Core Block Diagram........

  • Page 16

    Figure 8-1 Example of a DSP56800 Stack Frame ....... 8-29 Figure 9-1 JTAG/OnCE Interface Block Diagram.

  • Page 17

    Figure B-3 LMS Adaptive Filter—Single Precision Memory Map ......B-9 Figure B-4 LMS Adaptive Filter—Double Precision Memory Map ..... . . B-10 Figure B-5 LMS Adaptive Filter—Double Precision Delayed Memory Map .

  • Page 18

    DSP56800 Family Manual...

  • Page 19

    List of Examples Example 3-1 Loading an Accumulator with a Word for Integer Processing ... . . 3-11 Example 3-2 Reading a Word from an Accumulator for Integer Processing ... . 3-12 Example 3-3 Correctly Reading a Word from an Accumulator to a D/A .

  • Page 20

    Example B-1 Source Code Layout ..........B-1 DSP56800 Family Manual...

  • Page 21: About This Book

    About This Book This manual describes the central processing unit of the DSP56800 Family in detail. It is intended to be used with the appropriate DSP56800 Family member user’s manual, which describes the central processing unit, programming models, and details of the instruction set. The appropriate DSP56800 Family member technical data sheet provides timing, pinout, and packaging descriptions.

  • Page 22

    Chapter 8, “Software Techniques.” This section teaches the advanced user techniques for more efficient programming of the DSP56800 Family. It includes a description of useful instruction sequences and macros, optimal loop and interrupt programming, topics related to the stack of the DSP56800, and other useful software topics.

  • Page 23

    Conventions This document uses the following notational conventions: • Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). • Bits within a register are formatted AA[n:0] when more than one bit is involved in a description. For purposes of description, the bits are presented as if they are contiguous within a register.

  • Page 24

    DSP56800 Family Manual...

  • Page 25: Dsp56800 Family Architecture

    DSP56800 Family Architecture The DSP56800 Family uses the DSP56800 16-bit DSP core. This core is a general-purpose central processing unit (CPU), designed for both efficient DSP and controller operations. Its instruction-set efficiency as a DSP is superior to other low-cost DSP architectures and has been designed for efficient, straightforward coding of controller-type tasks.

  • Page 26: Core Overview

    The general-purpose nature of the instruction set also allows for an efficient compiler implementation. A variety of standard peripherals can be added around the DSP56800 core (see Figure 1-1 on page 1-1) such as serial ports, general-purpose timers, real-time and watchdog timers, different memory configurations (RAM, ROM, or both), and general-purpose I/O (GPIO) ports.

  • Page 27: Peripheral Blocks

    B2 B1 B0 OnCE AA0006 Figure 1-2. DSP56800 Core Block Diagram 1.1.2 Peripheral Blocks The following peripheral blocks are available for members of the DSP56800 16-bit Family: • Program ROM and RAM modules • Bootstrap ROM for program RAM parts •...

  • Page 28

    — Pins can be individually programmed as input or output — Pins can be individually multiplexed between peripheral functionality and GPIO — Pins can have interrupt capability More blocks will be defined in the future to meet customer needs. DSP56800 Family Manual...

  • Page 29: Family Members, Introduction To Digital Signal Processing

    1.1.3 Family Members The DSP56800 core processor is designed as a core processor for a family of Motorola DSPs. An example of a chip that can be built with this core is shown in Figure 1-3 on page 1-5. IRQA...

  • Page 30

    The equivalent circuit using a DSP is shown in Figure 1-5 on page 1-7. This application requires an analog-to-digital (A/D) converter and digital-to-analog (D/A) converter in addition to the DSP. Even with these additional parts, the component count can be lower using a DSP due to the high integration available with current components. DSP56800 Family Manual...

  • Page 31

    Introduction to Digital Signal Processing Low-Pass Sampler and DSP Operation Digital-to-Analog Reconstruction Anti-Aliasing Analog-to-Digital Converter Low-Pass Filter Converter FIR Filter ∑ c k ( ) × – y(t) x(t) x(n) y(n) Finite Impulse Response Analog In Analog Out Ideal Filter Frequency Analog Filter...

  • Page 32

    Self-test can be built in • Better power-supply rejection The DSP56800 Family is not a custom IC designed for a particular application; it is designed as a general-purpose DSP architecture to efficiently execute commonly used DSP benchmarks and controller code in minimal time.

  • Page 33: Summary Of Features

    Family of processors has a dual Harvard architecture optimized for MAC operations. Figure 1-6 on page 1-8 shows how the DSP56800 architecture matches the shape of the MAC operation. The two operands, c( ) and x( ), are directed to a multiply operation, and the result is summed. This process is built into the chip by allowing two separate data-memory accesses to feed a single-cycle MAC.

  • Page 34: For The Latest Information

    Two additional low power modes, stop and wait, further reduce power requirements. Wait is a low-power mode where the DSP56800 core is shut down but the peripherals and interrupt controller continue to operate so that an interrupt can bring the chip out of wait mode. In stop mode, even more of the circuitry is shut down for the lowest power-consumption mode.

  • Page 35: Core Block Diagram

    Core Block Diagram The DSP56800 core is composed of functional units that operate in parallel to increase the throughput of the machine. The program controller, AGU, and data ALU each contain their own register set and control logic, so each may operate independently and in parallel with the other two. Likewise, each functional unit interfaces with other units, with memory, and with memory-mapped peripherals over the core’s internal...

  • Page 36

    OnCE Figure 2-1. DSP56800 Core Block Diagram Note that Figure 2-1 illustrates two methods for connecting peripherals to the DSP56800 core: using the Motorola-standard IP-BUS interface or via a dedicated peripheral global data bus (PGDB). When the IP-BUS interface is used, peripheral registers may be memory mapped into any data (X) memory address range and are accessed with standard X-memory reads and writes.

  • Page 37: Data Arithmetic Logic Unit (alu), Address Generation Unit (agu)

    Core Block Diagram 2.1.1 Data Arithmetic Logic Unit (ALU) The data arithmetic logic unit (ALU) performs all of the arithmetic and logical operations on data operands. It consists of the following: • Three 16-bit input registers (X0, Y0, and Y1) •...

  • Page 38: Program Controller And Hardware Looping Unit

    The program controller is described in detail in Chapter 5, “Program Controller.” For more details on program looping, refer to Section 5.3, “Program Looping,” on page 5-14 and Section 8.6, “Loops,” on page 8-20. For information on reset and interrupts, refer to Chapter 7, “Interrupts and the Processing States.” DSP56800 Family Manual...

  • Page 39: Bus And Bit-manipulation Unit, On-chip Emulation (once) Unit, Address Buses, Data Buses

    The bit-manipulation unit performs bit-field manipulations on X (data) memory words, peripheral registers, and all registers within the DSP56800 core. It is capable of testing, setting, clearing, or inverting any bits specified in a 16-bit mask. For branch-on-bit-field instructions, this unit tests bits on the upper or lower byte of a 16-bit word (that is, the mask can only test up to 8 bits at a time).

  • Page 40: Memory Architecture

    There is also a support for a second read-only data path to data memory. In DSP56800 Family devices that implement this second bus, it is possible to initiate two simultaneous data read operations, allowing for a total of three parallel memory accesses.

  • Page 41: Blocks Outside The Dsp56800 Core, External Data Memory

    The following blocks are optionally found on DSP56800-based DSP chips and are considered peripheral and memory blocks, not part of the DSP56800 core. These and other blocks are described in greater detail in the appropriate chip-specific user’s manual. Figure 2-3 shows an example DSP56800-based device.

  • Page 42: Program Memory, Bootstrap Memory, Ip-bus Bridge, Phase Lock Loop (pll), Dsp56800 Core Programming Model

    DSP56800 Core Programming Model The registers in the DSP56800 core that are considered part of the DSP56800 core programming model are shown in Figure 2-4 on page 2-9. There may also be other important registers that are not included in the DSP56800 core, but mapped into the data address space.

  • Page 43

    16 15 16 15 Address Generation Unit Pointer Offset Modifier Registers Register Register Program Controller Unit Program Status Operating Mode Counter Register (SR) Register Hardware Stack (HWS) Loop Address Loop Counter AA0007 Figure 2-4. DSP56800 Core Programming Model Core Architecture Overview...

  • Page 44

    Core Architecture Overview 2-10 DSP56800 Family Manual...

  • Page 45

    Chapter 3 Data Arithmetic Logic Unit This chapter describes the architecture and the operation of the data arithmetic logic unit (ALU), the block where the multiplication, logical operations, and arithmetic operations are performed. (Addition can also be performed in the address generation unit, and the bit-manipulation unit can perform logical operations.) The data ALU contains the following: •...

  • Page 46: Overview And Architecture

    Instructions can access the register as a whole or by these individual portions (see Section 3.1.2, “Data ALU Accumulator Registers,” on page 3-4 and Section 3.2, “Accessing the Accumulator Registers,” on page 3-7). The blocks and registers within the data ALU are explained in the following sections. DSP56800 Family Manual...

  • Page 47

    Overview and Architecture XDB2 CGDB Optional Invert Arith/Logical Shifter SHIFTER/MUX 36-bit Accumulator Shifter Rounding Constant OMR’s SA Bit MAC Output Limiter EXT:MSP:LSP Condition Code Generation OMR’s CC Bit Condition Codes to Status Register Figure 3-1. Data ALU Block Diagram Data Arithmetic Logic Unit...

  • Page 48: Data Alu Input Registers (x0, Y1, And Y0), Data Alu Accumulator Registers

    DSP tasks, because this preserves the full precision of multiplication and other ALU operations. Data limiting and saturation are also possible using the full registers, in cases where the final result of a computation that has overflowed is moved (see Section 3.4.1, “Data Limiter,” on page 3-26). DSP56800 Family Manual...

  • Page 49: Multiply-accumulator (mac) And Logic Unit, Barrel Shifter

    Overview and Architecture Accessing an accumulator through its individual portions (A2, A1, A0, B2, B1, or B0) is useful for systems and control programming. When accumulators are manipulated using their constituent components, saturation and limiting are disabled. This allows for microcontroller-like 16-bit integer processing for non-DSP purposes.

  • Page 50: Accumulator Shifter, Data Limiter And Mac Output Limiter

    The MAC Output Limiter saturates the output of the data ALU’s MAC unit. Section 3.4, “Saturation and Data Limiting,” provides an in-depth discussion of saturation and limiting, as well as a description of the operation of the two limiter units. DSP56800 Family Manual...

  • Page 51: Accessing The Accumulator Registers, Table 3-1 Accessing The Accumulator Registers

    The DSP56800 instruction set transparently supports both methods of access. An entire accumulator may be accessed simply through the specification of the full-register name (A or B), while portions are accessed through the use of their respective names (A0, B1, and so on).

  • Page 52: Accessing An Accumulator By Its Individual Portions

    When F2 is written, the register receives the low-order portion of the word; the high-order portion is not used. See Figure 3-4. CGDB Bus Contents LSB of Not Used Word Register F2 Used No Bits Present Register F2 as a Destination Figure 3-4. Writing the Accumulator Extension Registers (F2) DSP56800 Family Manual...

  • Page 53

    Accessing the Accumulator Registers When F2 is read, the register contents occupy the low-order portion (bits 3–0) of the word; the high-order portion (bits 15–4) is sign extended. See Figure 3-5. Register F2 No Bits Present Register F2 Used as a Source LSB Of Word Sign Extension...

  • Page 54: Accessing An Entire Accumulator, Accessing For Data Alu Operations

    Limiting will be performed only when the entire 36-bit accumulator register (F) is specified as the source for a parallel data move or a register transfer. It is not performed when F2, F1 or F0 is specified. 3-10 DSP56800 Family Manual...

  • Page 55: Examples Of Writing The Entire Accumulator, General Integer Processing, Writing Integer Data To An Accumulator

    General integer and control processing typically involves manipulating 16- and 32-bit integer quantities. Rarely will such code use a full 36-bit accumulator such as that implemented by the DSP56800 Family. The architecture of the DSP56800 supports the manipulation of 16-bit integer quantities using the accumulators, but care must be taken when performing such manipulation.

  • Page 56: Reading Integer Data From An Accumulator, Using 16-bit Results Of Dsp Algorithms

    This is accomplished through sequentially saving and restoring the individual parts of the register, and not the whole register at once. See Example 3-4 on page 3-13. 3-12 DSP56800 Family Manual...

  • Page 57: Bit-field Operations On Integers In Accumulators, Converting From 36-bit Accumulator To 16-bit Portion

    Accessing the Accumulator Registers Example 3-4. Correct Saving and Restoring of an Accumulator—Word Accesses ; Saving the A Accumulator to the Stack (SP)+ ; Point to first empty location MOVE A2,X:(SP)+ ; Save extension register MOVE A1,X:(SP)+ ; Save F1 register MOVE A0,X:(SP) ;...

  • Page 58: Fractional And Integer Data Alu Arithmetic

    (E) of the status register. Refer to Section 5.1.8, “Status Register,” on page 5-6. Fractional and Integer Data ALU Arithmetic The ability to perform both integer and fractional arithmetic is one of the strengths of the DSP56800 architecture; there is a need for both types of arithmetic.

  • Page 59

    32-Bit Long Word Operand in A1,B1 36-Bit Accumulator Integer Two’s-Complement Representations AA0041 Figure 3-8. Bit Weightings and Operand Alignments The representation of numbers allowed on the DSP56800 architecture are as follows: • Two’s-complement values • Fractional or integer values •...

  • Page 60: Interpreting Data, Table 3-2 Interpretation Of 16-bit Data Values

    (decimal) (decimal) (decimal) $7 FFFF FFFF 34,359,738,367 ~ 16.0 $1 4000 0000 5,368,709,120 $0 4000 0000 1,073,741,824 16,384 $0 2000 0000 536,870,912 8,192 0.25 $0 0000 0000 $F C000 0000 - 1,073,741,824 - 16,384 - 0.5 3-16 DSP56800 Family Manual...

  • Page 61: Data Formats, Signed Fractional, Unsigned Fractional

    Fractional and Integer Data ALU Arithmetic Table 3-3. Interpretation of 36-bit Data Values (Continued) 36-Bit Integer in Fractional Hexadecimal 16-Bit Integer in MSP Entire Accumulator Value Representation (decimal) (decimal) (decimal) $F E000 0000 - 536,870,912 - 8,192 - 0.25 $E C000 0000 - 5,368,709,120 -2 .5 $8 0000 0001...

  • Page 62: Signed Integer, Unsigned Integer, Addition And Subtraction

    Fractional word-sized arithmetic would be performed in a similar manner. For arithmetic operations where the destination is a 16-bit register or memory location, the fractional or integer operation is correctly calculated and stored in its 16-bit destination. 3-18 DSP56800 Family Manual...

  • Page 63: Logical Operations, Multiplication, Fractional Multiplication

    For fractional and integer arithmetic, the logical operations (AND, OR, EOR, and bit-manipulation instructions) are performed identically. This means that any DSP56800 logical or bit-field instruction can be used for both fractional and integer values. Typically, logical operations are only performed on integer values, but there is no inherent reason why they cannot be performed on fractional values as well.

  • Page 64: Integer Multiplication

    16-bit signed integer operands using the IMPY(16) instruction gives a 16-bit signed integer result that is placed in the MSP (A1 or B1) of the accumulator. The corresponding extension register (A2 or B2) is filled with sign extension and the LSP (A0 or B0) remains unchanged. 3-20 DSP56800 Family Manual...

  • Page 65: Division

    Fractional and Integer Data ALU Arithmetic Input Operand 1 Input Operand 2 Signed Integer Input Operands 16 Bits 16 Bits 16 Bits Signed Intermediate Multiplier Result 31 Bits S Ext. Signed Integer Unchanged Output 16 Bits AA0044 Figure 3-12. Integer Multiplication (IMPY) At other times it is necessary to maintain the full 32-bit precision of an integer multiplication.

  • Page 66: Unsigned Arithmetic, Conditional Branch Instructions For Unsigned Operations, Unsigned Multiplication

    3.3.7 Unsigned Arithmetic Unsigned arithmetic can be performed on the DSP56800 architecture. The addition, subtraction, and compare instructions work for both signed and unsigned values, but the condition code computation is different. Likewise, there is a difference for unsigned multiplication.

  • Page 67: Multi-precision Operations, Multi-precision Addition And Subtraction, Multi-precision Multiplication

    ; Optionally convert to integer result 3.3.8 Multi-Precision Operations The DSP56800 instruction set contains several instructions which simplify extended- and multi-precision mathematical operations. By using these instructions, 64-bit and 96-bit calculations can be performed, and calculations involving different-sized operands are greatly simplified.

  • Page 68

    MOVE A2,A1 ; (note that A2 contains only sign ; extension) X0,Y1,A ; Single Precision x Upper Portion and add to Previous ; Convert result to integer, A2 contains sign extension ; (52-bit shift of A2:A1:A0:B1) 3-24 DSP56800 Family Manual...

  • Page 69

    Fractional and Integer Data ALU Arithmetic Example 3-16. Multiplying Two Fractional Double-Precision Values Signed 32x32 => 64 Multiplication Subroutine Parameters: R1 = ptr to lowest word of one operand R2 = ptr to lowest word of one operand R3 = ptr to where results are stored MULT_S32_X_S32 ;...

  • Page 70: Saturation And Data Limiting, Data Limiter

    Without saturation, the output data may incorrectly switch from a large positive number to a large negative value, which can cause problems for DAC outputs in embedded applications. The DSP56800 architecture supports optional saturation of results through two limiters found within the data ALU: •...

  • Page 71: Table 3-4 Saturation By The Limiter Using The Move Instruction

    Saturation and Data Limiting Once the accumulator increments to $8000 in Example 3-17, the positive result can no longer be written to a 16-bit memory location without overflow. So, instead of writing an overflowed value to memory, the value of the most positive 16-bit number, $7fff, is written instead by the data limiter block. Note that the data limiter block does not affect the accumulator;...

  • Page 72: Mac Output Limiter

    ; A = $0:7FFD:0000 ; A = $0:7FFE:0000 ; A = $0:7FFF:0000 ; A = $0:7FFF:FFFF <=== Saturates to 16-bits! ; A = $0:7FFF:FFFF <=== Saturates to 16-bits! #9,A ; A = $0:7FFF:FFFF <=== Saturates to 16-bits! 3-28 DSP56800 Family Manual...

  • Page 73: Instructions Not Affected By The Mac Output Limiter

    Saturation and Data Limiting Once the accumulator increments to $7FFF in Example 3-19, the saturation logic in the MAC Output limiter prevents it from growing larger because it can no longer fit into a 16-bit memory location without overflow. So instead of writing an overflowed value to back to the A accumulator, the value of the most positive 32-bit number, $7FFF:FFFF, is written instead as the arithmetic result.

  • Page 74: Rounding, Convergent Rounding

    The DSP core implements two types of rounding: convergent rounding and two’s-complement rounding. For the DSP56800, the rounding point is between bits 16 and 15 of a 36-bit value; for the A accumulator, it is between the A1 register’s LSB and the A0 register’s MSB. The usual rounding method rounds up any value above one-half (that is, LSP >...

  • Page 75: Two's-complement Rounding

    Rounding Case I : If A0 < $8000 (1/2), then round down (add nothing) Before Rounding After Rounding X X . . X X X X X . . . X X X 0 1 0 0 0 1 1 X X X ..X X X X X .

  • Page 76

    *A0 is always clear; performed during RND, MPYR, MACR AA0050 Figure 3-16. Two’s-Complement Rounding Once the rounding bit has been programmed in the OMR register, there is a delay of one instruction cycle before the new rounding mode becomes active. 3-32 DSP56800 Family Manual...

  • Page 77: Condition Code Generation, Bit Destinations—cc Bit Cleared

    Condition Code Generation Condition Code Generation The DSP core supports many different arithmetic instructions for both word and long-word operations. The flexible nature of the instruction set means that condition codes must also be generated correctly for the different combinations allowed. There are three questions to consider when condition codes are generated for an instruction: •...

  • Page 78: Bit Destinations—cc Bit Set, Bit Destinations—cc Bit Cleared

    Z is set if bits 31–16 of the corresponding accumulator are all cleared. • V is set if overflow has occurred in the 16-bit result. • C is set if a carry (borrow) has occurred out of bit 31 of the result. 3-34 DSP56800 Family Manual...

  • Page 79: Bit Destinations, Special Instruction Types

    Condition Code Generation 3.6.5 16-Bit Destinations Some arithmetic instructions can generate a result for a 36-bit accumulator or a 16-bit destination such as a register or memory location. When condition codes for a 16-bit destination are being generated, the CC bit is ignored and condition codes are generated using the 16 bits of the result.

  • Page 80: Tst And Tstw Instructions, Unsigned Arithmetic

    When arithmetic on unsigned operands is being performed, the condition codes used to compare two values differ from those used for signed arithmetic. See Section 3.3.7, “Unsigned Arithmetic,” for a discussion of condition code usage for unsigned arithmetic. 3-36 DSP56800 Family Manual...

  • Page 81

    Chapter 4 Address Generation Unit This chapter describes the architecture and the operation of the address generation unit (AGU). The address generation unit is the block where all address calculations are performed. It contains two arithmetic units—a modulo arithmetic unit for complex address calculations and an incrementer/decrementer for simple calculations.

  • Page 82: Architecture And Programming Model

    XAB2. The data memory, in turn, places its data on the core global data bus (CGDB) and the second external data bus (XDB2), respectively (see Figure 4-1 on page 4-3). See Section 6.1, “Introduction to Moves and Parallel Moves,” on page 6-1 for more discussion on parallel memory moves. DSP56800 Family Manual...

  • Page 83

    Architecture and Programming Model CGDB(15:0) Modulo Arithmetic Unit Inc./Dec. R3 Only PAB(15:0) XAB1(15:0) XAB2(15:0) AA0014 Figure 4-1. Address Generation Unit Block Diagram All four address pointer registers and the SP are used in generating addresses in the register indirect addressing modes. The offset register can be used by all four address pointer registers and the SP, whereas the modulo register can be used by the R0 or by both the R0 and R1 pointer registers.

  • Page 84: Address Registers (r0-r3), Stack Pointer Register (sp), Offset Register (n)

    CGDB. The offset register is used as input to the modulo arithmetic unit. It is often used for array indexing or indexing into a table, as discussed in Section 8.7, “Array Indexes,” on page 8-26. DSP56800 Family Manual...

  • Page 85: Modifier Register (m01), Modulo Arithmetic Unit, Incrementer/decrementer Unit

    Architecture and Programming Model NOTE: If the N address register is changed with a MOVE instruction, this register’s contents will be available for use on the immediately following instruction. In this case the instruction that writes the N address register will be stretched one additional instruction cycle.

  • Page 86: Addressing Modes, Table 4-1 Addressing Mode Forcing Operators, Table 4-2 Jump And Branch Forcing Operators

    Address Generation Unit Addressing Modes The DSP56800 instruction set contains a full set of operand addressing modes, optimized for high-performance signal processing as well as efficient controller code. All address calculations are performed in the address generation unit to minimize execution time.

  • Page 87: Register-direct Modes, Data Or Control Register Direct, Address Register Direct, Address-register-indirect Modes

    Addressing Modes 4.2.1 Register-Direct Modes The register-direct addressing modes specify that the operand is in one (or more) of the nine data ALU registers, seven address registers, or four control registers. The various options are shown in Table 4-3 on page 4-7.

  • Page 88: Table 4-4 Addressing Mode—address Register Indirect

    “indexed by short displacement” addressing mode. For instructions where two reads are performed from the X data memory, the second read using the R3 pointer must always be from on-chip memory. The addressed register sets are summarized in Table 4-5. DSP56800 Family Manual...

  • Page 89: No Update: (rn), (sp), Table 4-5 Address-register-indirect Addressing Modes Available

    The type of arithmetic to be performed is not encoded in the instruction, but it is specified by the address modifier register (M01 for the DSP56800 core). It indicates whether linear or modulo arithmetic is performed when doing address calculations. In the case where there is not a modifier register for a particular register set (R2 or R3), linear addressing is always performed.

  • Page 90

    16 15 X Memory X Memory $1000 $1000 $1000 $1000 (n/a) (n/a) (n/a) (n/a) Assembler syntax: X:(Rn), X:(SP) Additional instruction execution cycles: 0 Additional effective address program words: 0 AA0016 Figure 4-3. Address Register Indirect: No Update 4-10 DSP56800 Family Manual...

  • Page 91: Post-increment By 1: (rn)+, (sp)+

    Addressing Modes 4.2.2.2 Post-Increment by 1: (Rn)+, (SP)+ The address of the operand is in the address register Rn or SP. After the operand address is used, it is incremented by one and stored in the same address register. The type of arithmetic (linear or modulo) used to increment Rn is determined by M01 for R0 and R1 and is always linear for R2, R3, and SP.

  • Page 92: Post-decrement By 1: (rn)-, (sp)-

    X Memory X Memory $4735 $4735 $4734 $4734 $4735 $4734 (n/a) (n/a) $FFFF $FFFF Assembler syntax: X:(Rn)-, X:(SP)- Additional instruction execution cycles: 0 Additional effective address program words: 0 AA0018 Figure 4-5. Address Register Indirect: Post-Decrement 4-12 DSP56800 Family Manual...

  • Page 93: Post-update By Offset N: (rn)+n, (sp)+n

    Addressing Modes 4.2.2.4 Post-Update by Offset N: (Rn)+N, (SP)+N The address of the operand is in the address register Rn or SP. After the operand address is used, the contents of the N register are added to Rn and stored in the same address register. The content of N is treated as a two’s-complement signed number.

  • Page 94: Index By Offset N: (rn+n), (sp+n)

    X Memory $7003 $7003 $7000 $7000 $7000 $7000 $0003 $0003 $FFFF $FFFF Assembler syntax: X:(Rn+N), X:(SP+N) Additional instruction execution cycles: 1 Additional effective address program words: 0 AA0020 Figure 4-7. Address Register Indirect: Indexed by Offset N 4-14 DSP56800 Family Manual...

  • Page 95: Index By Short Displacement: (sp-xx), (r2+xx)

    Addressing Modes 4.2.2.6 Index by Short Displacement: (SP-xx), (R2+xx) This addressing mode contains the 6-bit short immediate index within the instruction word. This field is always one-extended to form a negative offset when the SP register is used and is always zero-extended to form a positive offset when the R2 register is used.

  • Page 96: Index By Long Displacement: (rn+xxxx), (sp+xxxx)

    $4567 $4567 $FFFF $FFFF Long Immediate Value from the Instruction Word Assembler syntax: X:(Rn+xxxx), X:(SP+xxxx) Additional instruction execution cycles: 2 Additional effective address program words: 1 AA0022 Figure 4-9. Address Register Indirect: Indexed by Long Displacement 4-16 DSP56800 Family Manual...

  • Page 97: Immediate Data Modes, Table 4-6 Addressing Mode—immediate

    Addressing Modes 4.2.3 Immediate Data Modes The immediate data modes specify the operand directly in a field of the instruction. That is, the operand value to be used is contained within the instruction word itself (or words themselves). There are two types of immediate data modes: immediate data, which uses an extension word to contain the operand, and immediate short data, where the operand is contained within the instruction word.

  • Page 98: Immediate Data: #xxxx

    : MOVE #$A987,B Before Execution After Execution 35 32 31 16 15 35 32 31 16 15 Assembler syntax: #xxxx Additional instruction execution cycles: 1 Additional effective address program words: 1 AA0023 Figure 4-10. Special Addressing: Immediate Data 4-18 DSP56800 Family Manual...

  • Page 99

    Addressing Modes Immediate Short into 16-Bit Address Register Example : MOVE #$0027,N Before Execution After Execution XXXX $0027 Immediate Short into 16-Bit Data Register Example : MOVE #$FFC6,X0 Before Execution After Execution XXXX $FFC6 Immediate Short into 16-Bit Accumulator Register Example : MOVE #$001C,B1 Before Execution After Execution...

  • Page 100: Immediate Short Data: #xx, Absolute Addressing Modes, Table 4-7 Addressing Mode—absolute

    Table 4-7. Addressing Mode—Absolute Addressing Mode: Notation in the Instruction Examples Absolute Set Summary Absolute short address—6 bit X:aa X:$0002 (direct addressing) X:<$02 I/O short address—6 bit X:pp X:$00FFE3 (direct addressing) X:<<$FFE3 Absolute address—16-bit X:xxxx X:$00F001 (extended addressing) X:>$C002 4-20 DSP56800 Family Manual...

  • Page 101: Absolute Address (extended Addressing): Xxxx

    Addressing Modes 4.2.4.1 Absolute Address (Extended Addressing): xxxx This addressing mode requires one word of instruction extension, which contains the 16-bit absolute address of the operand. No registers are used to form the address of the operand. Absolute address instructions are used with the bit-manipulation and move instructions. This reference is classified as a memory reference and a program reference.

  • Page 102: Absolute Short Address (direct Addressing):

    Before Execution After Execution $ABCD $ABCD X Memory X Memory $0003 $0003 $0000 $0000 Assembler syntax: X:<aa> Additional instruction execution cycles: 0 Additional effective address program words: 0 AA0026 Figure 4-13. Special Addressing: Absolute Short Address 4-22 DSP56800 Family Manual...

  • Page 103: I/o Short Address (direct Addressing): , Implicit Reference, Addressing Modes Summary

    Addressing Modes 4.2.4.3 I/O Short Address (Direct Addressing): <pp> For the I/O short addressing mode, the address of the operand occupies 6 bits in the instruction operation word and is one-extended. This allows direct access to the last 64 locations in X memory, which contain the on-chip peripheral registers.

  • Page 104: Table 4-8 Addressing Mode Summary

    The M01 modifier can only be used on the R0/N/M01 or R1/N/M01 register sets Hardware stack reference Program controller register reference Data ALU register reference Address Generation Unit register reference Program memory reference X memory reference Dual X memory read 4-24 DSP56800 Family Manual...

  • Page 105: Agu Address Arithmetic, Linear Arithmetic, Modulo Arithmetic, Modulo Arithmetic Overview

    Modulo Arithmetic Many DSP and standard control algorithms require the use of specialized data structures, such as circular buffers, FIFOs, and stacks. The DSP56800 architecture provides support for these algorithms by implementing modulo arithmetic in the address generation unit. 4.3.2.1 Modulo Arithmetic Overview To understand modulo address arithmetic, consider the example of a circular buffer.

  • Page 106

    R0 or R1 register with the low-order k bits all set to zero, effectively rounding the value down to the nearest multiple of 2 (64 in this case). This is shown in Figure 4-16 on page 4-27. 4-26 DSP56800 Family Manual...

  • Page 107: Configuring Modulo Arithmetic, Table 4-9 Programming M01 For Modulo Arithmetic

    AGU Address Arithmetic Memory $00B0 (Unavailable Addresses) Upper Boundary: $00A4 Lower Bound + Size - 1 = Upper Bound $009F Initial R0 Pointer Value Circular Buffer Lower Boundary: $0080 Lower Bound Relative to R0 Figure 4-16. Circular Buffer with Size M=37 When modulo arithmetic is performed on the buffer pointer register, only the low-order k bits are modified;...

  • Page 108

    NOTE: The reserved values ($0000, $4000-$8000, and $C000-$FFFE) should not be used. The behavior of the modulo arithmetic unit is undefined for these values, and may result in erratic program execution. 4-28 DSP56800 Family Manual...

  • Page 109: Supported Memory Access Instructions, Simple Circular Buffer Example

    AGU Address Arithmetic 4.3.2.3 Supported Memory Access Instructions The address generation unit supports modulo arithmetic for the following address-register-indirect modes: (Rn) (Rn)+ (Rn)- (Rn)+N (Rn+N) (Rn+xxxx) As noted in the preceding discussion, modulo arithmetic is only supported for the R0 and R1 address registers.

  • Page 110: Setting Up A Modulo Buffer

    — If modulo arithmetic is to be enabled for both the R0 and R1 address registers, be sure to set the high-order bit of M01: M01 = # locations - 1 + $8000 = 37 - 1 + 32768 = 32804 = $8024 4-30 DSP56800 Family Manual...

  • Page 111: Wrapping To A Different Bank

    AGU Address Arithmetic 2. Find the nearest power of two greater than or equal to the circular buffer size. In this ≥ 37, which gives us a value of k = 6. example, the value would be 2 3. From k, derive the characteristics of the lower boundary of the circular buffer. Since the “k” least-significant bits of the address of the lower boundary must all be 0s, then the buffer base address must be some multiple of 2 .

  • Page 112: Side Effects Of Modulo Arithmetic, When A Pointer Lies Outside A Modulo Buffer

    Side Effects of Modulo Arithmetic Due to the way modulo arithmetic is implemented by the DSP56800 Family, there are some side effects of using modulo arithmetic that must be kept in mind. Specifically, since the base address of a buffer must be a power of two, and since the modulo arithmetic unit can only detect a single wraparound, there are some restrictions and limitations that must be considered.

  • Page 113: Memory Locations Not Available For Modulo Buffers, Pipeline Dependencies

    Pipeline Dependencies 4.3.2.7.3 Memory Locations Not Available for Modulo Buffers For cases where the size of a buffer is not a power of two, there will be a range of memory locations immediately after the buffer that are not accessible with modulo addressing. Lower boundaries for modulo buffers always begin on an address where the lowest k bits are zeros—that is, a power of two.

  • Page 114

    For the case where a dependency is caused by a write to the M01 register, this sequence is not allowed and is flagged by the assembler. This sequence may be fixed by rearranging the instructions or inserting a NOP between the two instructions. 4-34 DSP56800 Family Manual...

  • Page 115

    Pipeline Dependencies Example 4-11. Dependency with a Write to the Modifier Register MOVE #$7,M01 ; Write to the M01 register MOVE X:(R0)+,X0 ; M01 register used in address ; arithmetic calculation In Example 4-12 there is a pipeline dependency since the SP register written in the first instruction is used by the immediately following JSR instruction to store the subroutine return address.

  • Page 116

    Address Generation Unit 4-36 DSP56800 Family Manual...

  • Page 117

    Chapter 5 Program Controller The program controller unit is one of the three execution units in the central processing module. The program controller performs the following: • Instruction fetching • Instruction decoding • Hardware DO and REP loop control • Exception (interrupt) processing This section covers the following: •...

  • Page 118

    HWS1 Control Signals Looping Control Interrupt Control Interrupt Request External Mode Select Pin(s) Control Bits to DSP Core Condition Codes from Data ALU Status and Control Bits to DSP Core AA0008 Figure 5-1. Program Controller Block Diagram DSP56800 Family Manual...

  • Page 119: Program Counter, Instruction Latch And Instruction Decoder, Interrupt Control Unit

    SR reflect the current IPL of the DSP core and indicate the level needed for an interrupt source to interrupt the processor. The DSP56800 core provides support for internal (on-chip) peripheral interrupts and two external interrupt sources, IRQA and IRQB. The interrupt control unit arbitrates between interrupt requests generated externally and by the on-chip peripherals.

  • Page 120: Looping Control Unit, Loop Counter

    DO loops in software. Note that since the LC is only a 13-bit counter, it is zero-extended when read; when written, the top three bits of the source word are ignored. This is shown in Figure 5-3 on page 5-5. DSP56800 Family Manual...

  • Page 121: Loop Address

    This register is not stacked by a DO instruction and not unstacked by end-of-loop processing, as is done on other Motorola DSPs. Section 5.3, “Program Looping,” discusses what occurs when the loop count is zero. See Section 8.6.4, “Nested Loops,” on page 8-22 for a discussion of nesting loops in software.

  • Page 122: Hardware Stack, Status Register

    (RTI). The program extension bits in the SR are restored from the stack by the return-from-subroutine (RTS) instruction—all other SR bits are unaffected. The SR format is shown in Figure 5-4 on page 5-7 and is also described in the following subsections. DSP56800 Family Manual...

  • Page 123: Carry (c)—bit 0, Overflow (v)—bit 1, Zero (z)—bit 2, Negative (n)—bit 3

    Architecture and Programming Model Mode Register (MR) Condition Code Register (CCR) Status Register Reset = $0300 Read/Write LF—Loop Flag I1,I0—Interrupt Mask SZ—Size L—Limit E—Extension U—Unnormalized N—Negative Z—Zero V—Overflow C—Carry * Indicates reserved bits that are read as zero and should be written with zero for future compatibility AA0011 Figure 5-4.

  • Page 124: Unnormalized (u)—bit 4, Extension (e)—bit 5, Limit (l)—bit 6, Size (sz)—bit 7

    Interrupt mask bit I0 must always be written with a one to ensure future compatibility and compatibility with other family members. The interrupt mask bits are set during processor reset. See Table 5-1 on page 5-9 for interrupt mask bit definitions. DSP56800 Family Manual...

  • Page 125: Reserved Sr Bits— Bits 10–14, Loop Flag (lf)—bit 15, Operating Mode Register

    Architecture and Programming Model Table 5-1. Interrupt Mask Bit Definition Exceptions Permitted Exceptions Masked (Reserved) (Reserved) IPL 0, 1 None (Reserved) (Reserved) IPL 1 IPL 0 5.1.8.10 Reserved SR Bits— Bits 10–14 The reserved SR bits 10–14 are reserved for future expansion and will read as zero during DSP read operations.

  • Page 126: Operating Mode Bits (mb And Ma)—bits 1–0, Table 5-2 Program Rom Operating Modes

    Internal Pmem disabled The exact implementation of the mode bits, and the number of modes supported, depends on the specific DSP56800 Family device being used. See the appropriate user’s manual for more detailed information on the operating modes. The bootstrap modes are used to initially load an on-chip program RAM upon exiting reset from external memory or through a peripheral.

  • Page 127: External X Memory Bit (ex)—bit 3, Saturation (sa)—bit 4, Table 5-3 Program Ram Operating Modes

    Architecture and Programming Model Table 5-3. Program RAM Operating Modes Program Memory Chip Operating Mode Reset Vector Configuration Single Chip Internal PROM P:$0000 Internal Pmem enabled (Reserved) (Reserved) (Reserved) Normal Expanded External Pmem P:$E000 Internal Pmem enabled Development External Pmem P:$0000 Internal Pmem disabled The MB and MA bit values are typically established on reset from an external input.

  • Page 128: Rounding Bit (r)—bit 5, Stop Delay Bit (sd)—bit 6, Condition Code Bit (cc)—bit 8

    Otherwise, the chip will not generate the unsigned conditions correctly. The effects of the CC bit on the condition codes generated by data ALU arithmetic operations are discussed in more detail in Section 3.6, “Condition Code Generation,” on page 3-33. 5-12 DSP56800 Family Manual...

  • Page 129: Nested Looping Bit (nl)—bit 15, Reserved Omr Bits—bits 2, 7 And 9–14, Software Stack Operation

    Software Stack Operation 5.1.9.7 Nested Looping Bit (NL)—Bit 15 The nested looping (NL) bit (OMR bit 15) is used to display the status of program DO looping and the hardware stack. If this bit is set, then the program is currently in a nested DO loop (that is, two DO loops are active).

  • Page 130: Program Looping, Repeat (rep) Looping

    The software stack is also used for nesting hardware DO loops in software on the DSP56800 architecture. On the DSP56800 architecture, the user must stack and unstack the LA and LC registers explicitly if DO loops are nested. In this case, the software stack is typically used for this purpose, as demonstrated in Section 8.6.4, “Nested Loops,”...

  • Page 131: Do Looping, Nested Hardware Do And Rep Looping, Terminating A Do Loop

    Program Looping 5.3.2 DO Looping The DO instruction is a two-word instruction that performs hardware looping on a block of instructions. It executes this block of instructions for the amount of times specified either with a 6-bit unsigned value or using the 13 least significant bits of a DSP core register.

  • Page 132

    Program Controller 5-16 DSP56800 Family Manual...

  • Page 133: Introduction To Moves And Parallel Moves

    Introduction to Moves and Parallel Moves To simplify programming, a powerful set of MOVE instructions is found on the DSP56800 core. This not only eases the task of programming the DSP, but also decreases the program code size and improves the efficiency, which in turn decreases the power consumption and MIPs required to perform a given task.

  • Page 134: Table 6-1 Memory Space Symbols

    DSP core registers that are most frequently accessed, including the registers in the data ALU, and all pointers in the address generation unit. For all moves on the DSP56800, the syntax orders the source and destination as follows: . The...

  • Page 135: Instruction Formats

    N register, and the R3 register is decremented by one. Both types of parallel moves use a subset of available DSP56800 addressing modes, and the registers available for the move portion of the instruction are also a subset of the total set of DSP core registers.

  • Page 136: Table 6-2 Instruction Formats

    Indicates data ALU, AGU, program controller, or bit-manipulation operation to be performed. Specifies the operands used by the opcode. Specifies optional data transfers over the CGDB bus. Specifies optional data transfers over the XDB2 bus. Specifies optional data transfers over the PDB bus. DSP56800 Family Manual...

  • Page 137: Programming Model

    Programming Model Programming Model The registers in the DSP56800 core programming model are shown in Figure 6-3. Data Arithmetic Logic Unit Data ALU Input Registers 16 15 Accumulator Registers 16 15 16 15 Address Generation Unit Pointer Offset Modifier Registers...

  • Page 138: Instruction Groups, Arithmetic Instructions, Table 6-3 Arithmetic Instructions List

    Table 6-3. Arithmetic Instructions List Instruction Description Absolute value Add long with carry Arithmetic shift left (36-bit) ASLL Arithmetic multi-bit shift left Arithmetic shift right (36-bit) ASRAC Arithmetic multi-bit shift right with accumulate ASRR Arithmetic multi-bit shift right DSP56800 Family Manual...

  • Page 139: Logical Instructions

    Instruction Groups Table 6-3. Arithmetic Instructions List (Continued) Instruction Description Clear Compare DEC(W) Decrement upper word of accumulator Divide iteration IMPY(16) Integer multiply INC(W) Increment upper word of accumulator Signed multiply-accumulate MACR Signed multiply-accumulate and round MACSU Signed/unsigned multiply-accumulate Signed multiply MPYR Signed multiply and round MPYSU...

  • Page 140: Bit-manipulation Instructions, Table 6-4 Logical Instructions List, Table 6-5 Bit-field Instruction List

    Table 6-5 lists the bit-manipulation instructions. Table 6-5. Bit-Field Instruction List Instruction Description ANDC Logical AND with immediate data BFCLR Bit-field test and clear BFSET Bit-field test and set BFCHG Bit-field test and change BFTSTL Bit-field test low DSP56800 Family Manual...

  • Page 141: Looping Instructions, Move Instructions, Table 6-6 Loop Instruction List

    Instruction Groups Table 6-5. Bit-Field Instruction List (Continued) Instruction Description BFTSTH Bit-field test high BRSET Branch if selected bits are set BRCLR Branch if selected bits are clear EORC Logical exclusive OR with immediate data NOTC Logical complement on memory location and registers Logical inclusive OR with immediate data NOTE: Due to instruction pipelining, if an AGU register (Rn, N, SP, or M01) is...

  • Page 142

    Instruction Set Introduction Table 6-35 on page 6-30 and are discussed in detail in Section 6.1, “Introduction to Moves and Parallel Moves,” and Appendix A, “Instruction Set Details.” The LEA instruction is also included in this instruction group. 6-10 DSP56800 Family Manual...

  • Page 143: Program Control Instructions, Table 6-7 Move Instruction List, Table 6-8 Program Control Instruction List

    STOP and WAIT instructions that can place the DSP chip in a low-power state. See Section 8.1.1, “Jumps and Branches,” on page 8-2 and Section 8.11, “Jumps and JSRs Using a Register Value,” on page 8-33 for additional jump and branch instructions that can be synthesized from existing DSP56800 instructions. Table 6-8 lists the program control instructions.

  • Page 144: Instruction Aliases, Andc, Eorc, Orc, And Notc Aliases

    6.5.1 ANDC, EORC, ORC, and NOTC Aliases The DSP56800 instruction set does not support logical operations using 16-bit immediate data. It is possible to achieve the same result, however, using the bit-manipulation instructions. To simplify implementing these operations, the DSP56800 assembler provides the following operations: •...

  • Page 145: Lsll Alias, Asl Alias, Clr Alias, Table 6-10 Lsll Instruction Alias

    Instruction Aliases Note that for the ANDC instruction, a one’s-complement of the mask value is used when remapping to the BFCLR instruction. For the NOTC instruction, all bits in the 16-bit mask are set to one. In Example 6-2, an immediate value is logically ORed with a location in memory. Example 6-2.

  • Page 146: Pop Alias, Dsp56800 Instruction Set Summary, Register Field Notation, Table 6-12 Clear Instruction Alias

    Simply decrements the SP DSP56800 Instruction Set Summary This section presents the entire DSP56800 instruction set in tabular form. The tables provide a quick reference to the entire instruction set because they show not only the instructions themselves, but also the registers, addressing modes, cycle counts, and program words required for each instruction.

  • Page 147: Table 6-14 Register Fields For General-purpose Writes And Reads

    DSP56800 Instruction Set Summary In some cases, the notation used when specifying an accumulator determines whether or not saturation is enabled when the accumulator is being used as a source in a move or parallel move instruction. Refer to Section 3.4.1, “Data Limiter,” on page 3-26 and Section 3.2, “Accessing the Accumulator Registers,” on page 3-7 for information.

  • Page 148: Using The Instruction Summary Tables, Table 6-16 Data Alu Registers

    -X0,Y0,A; A - (X0*Y0) -> A As an example, Table 6-35 on page 6-30 shows all registers and addressing modes that are allowed when performing a dual read instruction, one of the DSP56800’s parallel move instructions. The instructions shown in Example 6-3 are allowed.

  • Page 149: Instruction Summary Tables

    6.6.3 Instruction Summary Tables A summary of the entire DSP56800 instruction set is presented in this section in tabular form. In these tables, Table 6-17 on page 6-18 through Table 6-35 on page 6-30, the instructions are broken into several different categories and then listed alphabetically.

  • Page 150: Table 6-17 Move Word Instructions

    Refer to I/O Short Address MOVEP X:<<pp (Direct Addressing): <pp> on page 4-23 MOVE HHHH X:aa X:aa represents a 6-bit absolute address. Refer to Absolute Short Address (Direct MOVES X:<aa Addressing): <aa> on page 4-22 6-18 DSP56800 Family Manual...

  • Page 151: Table 6-18 Immediate Move Instructions, Table 6-19 Register-to-register Move Instructions

    DSP56800 Instruction Set Summary Table 6-18. Immediate Move Instructions Operation Source Destination Comments MOVE HHHH Signed 7-bit integer data (data is put in the lowest 7 bits of the word portion of any accumulator, upper 8 MOVEI bits and extension reg are sign extended, LSP por- tion is set to “0”)

  • Page 152: Table 6-21 Conditional Register Transfer Instructions, Table 6-22 Data Alu Multiply Instructions

    (±)Y1,X0,FDD Fractional multiply where one operand is (±)Y0,X0,FDD optionally negated before multiplication (±)Y1,Y0,FDD (±)Y0,Y0,FDD (±)A1,Y0,FDD Note: Assembler also accepts first two oper- (±)B1,Y1,FDD ands when they are specified in opposite order 6-20 DSP56800 Family Manual...

  • Page 153: Table 6-23 Data Alu Extended Precision Multiplication Instructions, Table 6-24 Data Alu Arithmetic Instructions

    DSP56800 Instruction Set Summary Table 6-22. Data ALU Multiply Instructions (Continued) Operation Operands Comments MPYR (±)Y1,X0,FDD Fractional multiply where one operand is (±)Y0,X0,FDD optionally negated before multiplication. Result (±)Y1,Y0,FDD is rounded (±)Y0,Y0,FDD (±)A1,Y0,FDD Note: Assembler also accepts first two oper- (±)B1,Y1,FDD...

  • Page 154

    X:xxxx,FDD on page 4-22 #xx,FDD Subtract an immediate value 0–31. #xxxx,FDD Subtract a signed 16-bit immediate. DD,F Transfer register to register. Transfer one accumulator to another (36-bits). Transfer one accumulator to another (36-bits). Test 36-bit accumulator. 6-22 DSP56800 Family Manual...

  • Page 155: Table 6-25 Data Alu Miscellaneous Instructions, Table 6-26 Data Alu Logical Instructions

    DSP56800 Instruction Set Summary Table 6-24. Data ALU Arithmetic Instructions (Continued) Operation Operands Comments TSTW DDDDD Test 16-bit word in register. All registers allowed (except HWS) except HWS. Limiting is not performed if an accumula- tor is specified. X:(Rn) Test a word in memory using appropriate addressing mode.

  • Page 156: Table 6-27 Data Alu Shifting Instructions

    A1,Y0,FDD B1,Y1,FDD LSRAC Y1,X0,F Logical word shifting with accumulation Y0,X0,F Y1,Y0,F Y0,Y0,F A1,Y0,F B1,Y1,F Rotate 16-bit register left by 1 bit through the carry bit Rotate 16-bit register right by 1 bit through the carry bit 6-24 DSP56800 Family Manual...

  • Page 157: Table 6-28 Agu Arithmetic Instructions, Table 6-29 Bit-manipulation Instructions

    DSP56800 Instruction Set Summary Table 6-28. AGU Arithmetic Instructions Operation Operands Comments (Rn)+ Increment the Rn pointer register (Rn)- Decrement the Rn pointer register (Rn)+N Add N index register to the Rn register and store the result in the Rn register...

  • Page 158: Table 6-30 Branch On Bit-manipulation Instructions

    MASK8 specifies a 16-bit immediate value where either the upper or lower 8 bits contains all zeros. AA specifies a 7-bit PC relative offset. X:aa represents a 6-bit absolute address. X:pp represents a 6-bit absolute I/O address. 6-26 DSP56800 Family Manual...

  • Page 159: Table 6-31 Change Of Flow Instructions, Table 6-32 Looping Instructions

    DSP56800 Instruction Set Summary Table 6-30. Branch on Bit-Manipulation Instructions (Continued) Operation Operands Comments BRSET #MASK8,DDDDD,AA 10/8 BRSET tests all bits selected by the immediate mask. If all selected bits are set, then the carry bit #MASK8,X:(R2+xx),AA 12/10 is set and a PC relative branch occurs. Otherwise...

  • Page 160: Table 6-33 Control Instructions

    No operation. STOP Enter STOP low-power mode. Execute the trap exception at the highest interrupt priority level, level 1 (non-maskable). WAIT Enter WAIT low-power mode. 6-28 DSP56800 Family Manual...

  • Page 161: Table 6-34 Data Alu Instructions—single Parallel Move

    DSP56800 Instruction Set Summary Table 6-34. Data ALU Instructions—Single Parallel Move Data ALU Operation Parallel Memory Move Operation Operands Source Destination Y1,X0,F X:(Rj)+ Y0,X0,F X:(Rj)+N MACR Y1,Y0,F MPYR Y0,Y0,F A1,Y0,F B1,Y1,F X0,F X:(Rj)+ Y1,F X:(Rj)+N Y0,F INC or INCW DEC or DECW Each instruction in Table 6-34 requires one program word and executes in one cycle.

  • Page 162: The Instruction Pipeline, Instruction Processing, Table 6-35 Data Alu Instructions—dual Parallel Read

    Figure 6-4 demonstrates pipelining; F1, D1, and E1 refer to the fetch, decode, and execute operations, respectively, of the first instruction. Note that the third instruction contains an instruction extension word and takes two cycles to execute. 6-30 DSP56800 Family Manual...

  • Page 163: Memory Access Processing

    The Instruction Pipeline Fetch Decode Execute Instruction Cycle Figure 6-4. Pipelining Each instruction requires a minimum of three instruction cycles (six machine cycles) to be fetched, decoded, and executed. A new instruction may be started after two machine cycles, making the throughput rate to be one instruction executed every instruction cycle for single-cycle instructions.

  • Page 164

    Instruction Set Introduction 6-32 DSP56800 Family Manual...

  • Page 165: Reset Processing State, Table 7-1 Processing States

    Chapter 7 Interrupts and the Processing States The DSP56800 Family processors have six processing states and are always in one of these states (see Table 7-1). Each processing state is described in detail in the following sections except the debug processing state, which is discussed in Section 9.3, “OnCE Port,”...

  • Page 166: Normal Processing State, Instruction Pipeline Description

    The processor fetches only one instruction word per instruction cycle; if an instruction is two words in length, it fetches the additional word with an additional cycle before it fetches the next instruction. DSP56800 Family Manual...

  • Page 167: Instruction Pipeline With Off-chip Memory Accesses, Table 7-2 Instruction Pipelining

    Normal Processing State Table 7-2. Instruction Pipelining Instruction Cycle Operation • • • Fetch • • • Decode • • • Execute • • • Table 7-2 demonstrates pipelining. “F1,” “D1,” and “E1” refer to the fetch, decode, and execute operations of the first instruction, respectively.

  • Page 168: Instruction Pipeline Dependencies And Interlocks, Table 7-3 Additional Cycles For Off-chip Memory Accesses

    EX bit (which changes the memory map) in the ORC’s execution time slot. The following code produces the expected results of reading the external ROM: ORC #$0008,OMR ; Sets EX bit at execution time slot ; Delays the MOVE so it will read the updated memory map MOVE X:$17,A ; Reads external memory DSP56800 Family Manual...

  • Page 169: Exception Processing State, Sequence Of Events In The Exception Processing State

    There are many sources for interrupts on the DSP56800 Family of chips, and some of these sources can generate more than one interrupt. Interrupt requests can be generated from conditions within the DSP core, from the DSP peripherals, or from external pins.

  • Page 170

    Recognized $0101 MACR JSR Instruction MOVE $0102 in Vector Table to $000E Interrupt Service $000F $0300 $0103 Routine $0104 $0300 $0105 $0301 $0106 — Explicit Return $0302 MOVE from Interrupt Recognized $0303 AA0056 Figure 7-1. Interrupt Processing DSP56800 Family Manual...

  • Page 171: Reset And Interrupt Vector Table, Table 7-4 Dsp56800 Core Reset And Interrupt Vector Table

    DSP core as well as all peripherals that can generate an interrupt. Table 7-4 lists the reset and interrupt vectors available on DSP56800-based DSP chips. The interrupt vectors used by on-chip peripherals, or by additional device-specific interrupt will be listed in the user’s manual for that chip.

  • Page 172: Interrupt Priority Structure, Configuring Interrupt Sources, Table 7-5 Interrupt Priority Level Summary

    7.3.4 Configuring Interrupt Sources The interrupt unit in the DSP56800 core supports seven interrupt channels for use by on-chip peripherals, in addition to the IRQ interrupts and interrupts generated by the DSP core. Each maskable interrupt source can individually be enabled or disabled as required by the application. The exact method for doing so is dependant on the particular DSP56800-based device, as some of the interrupt handling logic is implemented as an on-chip peripheral.

  • Page 173: Interrupt Sources

    Exception Processing State Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 IRQA Mode IRQB Mode (Reserved) Channel 6 IPL Channel 5 IPL Channel 4 IPL Channel 3 IPL Channel 2 IPL Channel 1 IPL Channel 0 IPL * Indicates reserved bits, read as zero and should be written with zero for future compatibility AA0057 Figure 7-2.

  • Page 174: External Hardware Interrupt Sources

    It is important that the interrupt service routine poll each device, and, after finding the source of the interrupt, it must clear the conditions causing the interrupt request. 7-10 DSP56800 Family Manual...

  • Page 175: Dsp Core Hardware Interrupt Sources, Dsp Core Software Interrupt Sources

    Exception Processing State 7.3.5.2 DSP Core Hardware Interrupt Sources Other interrupt sources include the following: • Stack error interrupt—priority level 1 • OnCE trap—priority level 1 • All on-chip peripherals (such as timers and serial ports)—priority level 0 An overflow of the hardware stack (HWS) causes a stack overflow interrupt that is vectored to P:$000A (see Section 5.1.7, “Hardware Stack,”...

  • Page 176: Interrupt Arbitration

    Each external and internal interrupt has its own flag. After each instruction is executed, the DSP arbitrates all interrupts. During arbitration, each pending interrupt’s IPL is compared with the interrupt mask in the SR, and the interrupt is either allowed or disallowed. The remaining pending 7-12 DSP56800 Family Manual...

  • Page 177: Table 7-7 Fixed Priority Structure Within An Ipl

    Exception Processing State interrupts are prioritized according to the IPLs shown in Table 7-7, and the interrupt source with the highest priority is selected. The interrupt vector corresponding to that source is then placed on the program address bus so that the program controller can fetch the interrupt instruction. Table 7-7.

  • Page 178: The Interrupt Pipeline

    Whenever a level 0 interrupt has been recognized and exception processing begins, the DSP56800 interrupt controller changes the interrupt mask bits in the program controller’s SR to allow only level 1 interrupts to be recognized.

  • Page 179

    Exception Processing State Interrupt Interrupt Vector Table Subroutine Main Program Interrupt PC Resumes Synchronized Operation Jump Address Interrupts Recognized Re-enabled as Pending Interrupt Routine Explicit Return From Interrupt (Should Be RTI) (a) Instruction Fetches from Memory Interrupt Synchronized and Recognized as Pending Interrupts Re-enabled Interrupt Control Cycle 1 Interrupt Control Cycle 2...

  • Page 180: Interrupt Latency

    LC is decremented to one (see Figure 7-7). During the execution of n2 in Figure 7-7, no interrupts will be serviced. When LC finally decrements to one, the fetches are re-initiated, and pending interrupts can be serviced. 7-16 DSP56800 Family Manual...

  • Page 181: Wait Processing State

    Wait Processing State Interrupt Main Synchronized and Program Recognized Fetches as Pending Repeat m n1 REP m Times Instruction N2 Replaced Per The REP Instruction Interrupts Re-enabled Interrupt Service Routine Fetches (From Between P:$0000 And P:$003F) i= Interrupt Instruction n= Normal Instruction (a) Instruction Fetches from Memory Interrupt Synchronized and Recognized as Pending...

  • Page 182

    — — Execute WAIT — — — — — — — Instruction Cycle Count i= Interrupt ii= Interrupt Instruction Word n= Normal Instruction Word Equivalent to Eight NOPs AA0075 Figure 7-9. Simultaneous Wait Instruction and Interrupt 7-18 DSP56800 Family Manual...

  • Page 183: Stop Processing State

    Stop Processing State Stop Processing State The STOP instruction brings the processor into the stop processing state, which is the lowest power-consumption state. In the stop state the clock oscillator is gated off, whereas in the wait state the clock oscillator remains active. The chip clears all peripheral interrupts and external interrupts (IRQA, IRQB, and NMI) when it enters the stop state.

  • Page 184

    3. Execute the STOP instruction and enter the stop state. 4. Recover from the stop state by asserting the IRQA pin and holding it asserted for the entire clock recovery time. If it is low, the IRQA vector will be fetched. 7-20 DSP56800 Family Manual...

  • Page 185

    Stop Processing State 5. The exact elapsed time for clock recovery is unpredictable. The external device that asserts IRQA must wait for some positive feedback, such as specific memory access or a change in some predetermined I/O pin, before deasserting IRQA. The STOP sequence totals 131,104 T cycles (if the SD equals 0) or 48 T cycles (if the SD equals 1) in addition to the period with no clocks from the stop fetch to the IRQA vector fetch (or next instruction).

  • Page 186: Debug Processing State

    Serial data is shifted in and out of this port, and it is possible to execute single instructions from this processing state. The debug processing state and the operation of the OnCE port is covered in more detail in Chapter 9, “JTAG and On-Chip Emulation (OnCE™).” 7-22 DSP56800 Family Manual...

  • Page 187: Useful Instruction Operations, Table 8-1 Operations Synthesized Using Dsp56800 Instructions

    Multi-tasking and the HWS Useful Instruction Operations The flexible instruction set of the DSP56800 architecture allows new instructions to be synthesized from existing DSP56800 instructions. This section presents some of these useful operations that are not directly supported by the DSP56800 instruction set, but can be efficiently synthesized. Table 8-1 lists operations that can be synthesized using DSP56800 instructions.

  • Page 188: Jumps And Branches, Jrset And Jrclr Operations

    Software Techniques Table 8-1. Operations Synthesized Using DSP56800 Instructions (Continued) Operation Description JVS, JVC, BVS, BVC Jumps or branches if the overflow bit is set or clear JPL, JMI, JES, JEC, JLMS, JLMC, Jumps or branches on other condition codes...

  • Page 189: Br1set And Br1clr Operations, Jr1set And Jr1clr Operations

    Useful Instruction Operations 8.1.1.2 BR1SET and BR1CLR Operations The BR1SET and BR1CLR operations are very similar to the BRSET and BRCLR instructions. They still test a bit field and branch to another address based on the result of some test. The difference is that for BRSET and BRCLR the condition is true if all selected bits in the bit field are 1s or 0s, respectively, whereas for BR1SET and BR1CLR the condition is true if at least one of the selected bits in the bit field is a 1 or 0, respectively.

  • Page 190: Jvs, Jvc, Bvs, And Bvc Operations, Other Jumps And Branches On Condition Codes, Negation Operations

    ; Operates on EXT:MSP, Clears LSP, 3 Icyc MOVE #0,A0 ; Clear LSP ; Now negates upper 20 bits of accumulator ; since A0 = 0 This correctly negates the upper 20 bits of the accumulator, but also destroys the A0 register. DSP56800 Family Manual...

  • Page 191: Negating The X0, Y0, Or Y1 Data Alu Registers, Negating An Agu Register

    Useful Instruction Operations The NEG instruction can be used directly, executing in one instruction cycle, in cases where it is already known that the least significant portion (LSP) of an accumulator is $0000. This is true immediately after a value is moved to the A or B accumulator from memory or a register, as shown in the following code: ;...

  • Page 192: Register Exchanges, Minimum And Maximum Values, Max Operation

    MAX Operation The MAX operation can be emulated as shown in the following code: ; MAX Operation X0,A ------ becomes ------ ; MAX operation ; Emulated at 4 Icyc X0,A X0,A ; (can also use TGE if desired) DSP56800 Family Manual...

  • Page 193: Min Operation, Accumulator Sign Extend, Unsigned Load Of An Accumulator

    ; Emulated at 2 Icyc MOVE x:(R0),A ZERO ------ becomes ------ ; DSP56800 Family Unsigned Load ; Emulated at 2 Icyc MOVE x:(R0),A1 This operation is important for processing unsigned numbers when the CC bit in the operating mode register (OMR) register is a 0, so that the condition codes are set using information at bit 35. This operation is useful for performing unsigned additions and subtractions on 36-bit values.

  • Page 194: And 32-bit Shift Operations, Small Immediate 16- Or 32-bit Shifts, General 16-bit Shifts

    Software Techniques 16- and 32-Bit Shift Operations This technique presents many different methods for performing shift operations on the DSP56800 architecture. Different techniques offer different advantages. Some techniques require several registers, while others can be performed only on the register to be shifted. It is even possible to shift the value in one register but place the result in a different register.

  • Page 195: General 32-bit Arithmetic Right Shifts, General 32-bit Logical Right Shifts

    16- and 32-Bit Shift Operations 8.2.3 General 32-Bit Arithmetic Right Shifts It is possible to perform right shifting of up to 15 bits on 32-bit values using the techniques presented in this section. The following example shows how to arithmetically shift the 32-bit contents of the Y1:Y0 registers, storing the results into the A accumulator.

  • Page 196: Arithmetic Shifts By A Fixed Amount, Right Shifts (asr12–asr20)

    If desired, it is possible to use this technique for bit shifts greater than 20, but it is not possible to use this technique for shifts of 11 or fewer bits without losing information. 8-10 DSP56800 Family Manual...

  • Page 197

    16- and 32-Bit Shift Operations ; ASR12 Operation ; Emulated in 8 Icyc, 8 Instruction Words PUSH ; (PUSH is a 2-word, 2 Icyc macro) MOVE A2,A ; ASR13 Operation ; Emulated in 7 Icyc, 7 Instruction Words PUSH ; (PUSH is a 2-word, 2 Icyc macro) MOVE A2,A ;...

  • Page 198: Left Shifts (asl16–asl19)

    ; Emulated in 6 Icyc, 6 Instruction Words PUSH ; (PUSH is a 2-word, 2 Icyc macro) MOVE A0,A ; ASL19 Operation ; Emulated in 7 Icyc, 7 Instruction Words PUSH ; (PUSH is a 2-word, 2 Icyc macro) MOVE A0,A 8-12 DSP56800 Family Manual...

  • Page 199: Incrementing And Decrementing Operations, Division

    Division It is possible to perform fractional or integer division on the DSP56800 core. There are several questions to consider when implementing division on the DSP core: •...

  • Page 200: Positive Dividend And Divisor With Remainder

    ;(At this point, the positive quotient is in ; B0 but the remainder is not yet correct) X0,B ;Restore remainder in B1 ;Required for correct integer remainder ;(At this point, the correct positive ; remainder is in B1) 8-14 DSP56800 Family Manual...

  • Page 201: Signed Dividend And Divisor With No Remainder

    Division 8.4.2 Signed Dividend and Divisor with No Remainder The algorithms in the following code provide fast ways to divide two signed, two’s-complement numbers. These algorithms are faster because they generate the quotient only; they do not generate a correct remainder.

  • Page 202: Signed Dividend And Divisor With Remainder

    4 quadrant division because these algorithms allow any combination of positive or negative operands for the dividend and divisor. One algorithm is presented for division of fractional numbers and a second is presented for the division of integer numbers. 8-16 DSP56800 Family Manual...

  • Page 203

    Division ; Four-Quadrant Division of Fractional, Signed Data (B1:B0 / X0) ; Generates signed quotient and remainder ; Setup MOVE B1,A ;Save sign bit of dividend (B1) in MSB of A1 MOVE B1,N ;Save sign bit of dividend (B1) in MSB of N ;Force dividend positive X0,Y1 ;Save sign bit of quotient in N bit of SR...

  • Page 204: Algorithm Examples

    = $7918 = 31000 The results can be easily checked by multiplying the quotient by the divisor and adding the remainder to this product. The final answer should be the same as the original dividend. 8-18 DSP56800 Family Manual...

  • Page 205: Overflow Cases, Multiple Value Pushes

    16-bit integer value. Otherwise, to prevent this from occurring, it is first necessary to scale the numerator. Multiple Value Pushes The DSP56800 core currently supports a one-word, one-instruction-cycle POP instruction for removing information from the stack. The PUSH operation, however, is a two-word, two-instruction-cycle macro, which expands to the following code.

  • Page 206: Loops, Large Loops (count Greater Than 63)

    When necessary, specifying an immediate value larger than 63 is done using one of the registers on the DSP56800 core to specify the loop count. Since registers are a precious resource, it is desirable not to use any important registers that may contain valid data. The following code shows a technique for specifying loop counts greater than 63 without destroying any register values.

  • Page 207: Variable Count Loops, Software Loops

    However, there is a limitation when the hardware looping mechanism is used. The DSP56800 allows a maximum of two nested hardware DO loops. Any looping beyond this generates a HWS overflow interrupt.

  • Page 208: Nested Loops, Recommendations

    1. The DSP56800 allows only two nested hardware DO loops. 2. The execution time of an outer hardware loop is comparable to the execution time of a software loop.

  • Page 209: Nested Hardware Do And Rep Loops

    8.6.4.2 Nested Hardware DO and REP Loops Nesting of hardware DO loops is permitted on the DSP56800 architecture. However, it is not recommended that this technique be used for nesting loops within a program. Rather, it is recommended that the hardware nesting of DO loops be used to provide more efficient interrupt processing, as described in Section 8.6.4.1, “Recommendations.”...

  • Page 210: Comparison Of Outer Looping Techniques

    Instead, it is recommended that all outer loops in a nested looping scheme be implemented using software looping techniques. Likewise, it is recommended that software looping techniques be used when a loop contains a JSR and the called routine contains many instructions or contains a hardware DO loop. 8-24 DSP56800 Family Manual...

  • Page 211: Hardware Do Looping In Interrupt Service Routines, Early Termination Of A Do Loop

    Loops 8.6.5 Hardware DO Looping in Interrupt Service Routines Upon entering an ISR, it is possible that one or two hardware DO loops are currently in progress. This means that the hardware looping resources (the LA and LC registers and the HWS) are currently in use and may need to be freed up if hardware looping is required within the ISR.

  • Page 212: Array Indexes, Global Or Fixed Array With A Constant

    ; Restore outer loop registers if nested loop Array Indexes The flexible set of addressing modes on the DSP56800 architecture allow for several different ways to index into arrays. Array indexing usually involves a base address and an offset from this base. The base address is the address of the first location in the array, and the offset indicates the location of the data in the array.

  • Page 213: Global Or Fixed Array With A Variable, Local Array With A Constant

    Array Indexes 8.7.2 Global or Fixed Array with a Variable This type of array indexing is performed with the X:(Rn+xxxx), X:(R2+xx), or X:(Rn+N) addressing mode. In the first two addressing modes—X:(Rn+xxxx) and X:(R2+xx)—the constant value specifies the base address of the array, and Rn or R2 specifies the offset into the array. These first two are similar to the method used by microcontrollers and are useful when only one or two accesses are performed with a particular base address, because it is not necessary to load a register with the base address.

  • Page 214: Parameters And Local Variables

    JSR instruction. These locations are then accessed using the DSP56800’s stack addressing modes. For the case of local variables, the value of the stack pointer is updated to accommodate the local variables. For example, if five local variables are to be allocated, then the stack pointer is increased by the value of five to allocate space on the stack for these local variables.

  • Page 215: Time-critical Do Loops

    However, sometimes the registers already contain data that is not necessary for the critical loop but must not be lost. In this case the DSP56800 architecture provides a convenient mechanism for freeing up these registers using the software stack. The programmer pushes any registers containing values not required in the tight loop, freeing up these registers for use.

  • Page 216: Interrupts, Setting Interrupt Priorities In Software

    8.10 Interrupts The interrupt mechanism on the DSP56800 is simple, yet flexible. There are two levels of interrupts: maskable and non-maskable. All maskable interrupts on the chip can be masked at one spot in the SR. Likewise, individual peripherals can be individually masked within one register, within the interrupt priority register (IPR), or at the peripheral itself.

  • Page 217: High Priority Or A Small Number Of Instructions, Many Instructions Of Equal Priority

    This is also recommended for ISRs with a very high priority, which should not be interrupted by some other source. ; Interrupt Service Routine ; DSP56800 core (Interrupts Remain Masked, 9 Overhead Cycles) ; located in interrupt vector table ; Long ISR (interrupt code) 8.10.1.2...

  • Page 218: Many Instructions And Programmable Priorities, Hardware Looping In Interrupt Routines

    For ISRs that require a significant number of instruction cycles to complete, it is possible for the user to still program interrupt priorities in software. This is shown in the following generic ISR. ; Generic ISR - DSP56800 core (20 Overhead Cycles) ; Instr located in Interrupt Vector Table (instructions) ;...

  • Page 219: Jumps And Jsrs Using A Register Value

    Jumps and JSRs Using a Register Value 8.11 Jumps and JSRs Using a Register Value Sometimes it is necessary to perform a jump or a jump to subroutine using the value stored in an on-chip register instead of using an absolute address. The RTS instruction is used to perform this task because it takes the value on the software stack and loads it into the program counter, effectively performing a jump.

  • Page 220: Freeing One Hardware Stack Location, Multitasking And The Hardware Stack

    HWS, contained in the NL and LF bits of the OMR and SR, respectively. Each read of the HWS register pops the HWS one value, and each write of the HWS register pushes the HWS one value. 8-34 DSP56800 Family Manual...

  • Page 221: Saving The Hardware Stack, Restoring The Hardware Stack

    Multitasking and the Hardware Stack 8.13.1 Saving the Hardware Stack An example of reading the entire contents of the HWS to X memory is shown in the following code: ; Save HWS ; 4 Icyc, 4 words MOVE SR,X:(R2)+ ; Read HWS pointer’s LSB (LF) and ;...

  • Page 222

    Software Techniques 8-36 DSP56800 Family Manual...

  • Page 223: Combined Jtag And Once Interface

    The OnCE port is a Motorola-designed module used to debug application software used with the chip. The port is a separate on-chip block that allows non-intrusive interaction with the DSP and is accessible through the pins of the JTAG interface.

  • Page 224: Jtag Port

    (TAP) that is fully compatible with this standard, commonly referred to as the “JTAG port.” This section provides an overview of the capabilities of the JTAG port as implemented on the DSP56800. Information provided here is intended to supplement the supporting IEEE 1149.1a-1993 document, which outlines the internal details, applications, and overall methodology of the standard.

  • Page 225: Jtag Capabilities, Jtag Port Architecture

    The JTAG module consists of the logic necessary to support boundary scan testing as defined in the IEEE specification. Although tightly coupled to the DSP56800’s core logic, it is an independent module, and, when disabled, it is guaranteed to have no impact on the function of the core.

  • Page 226: Once Port

    OnCE port. Commands sent to the JTAG module are decoded and processed by the command decoder. Commands for the JTAG port are completely independent from the DSP56800 instruction set, and are executed in parallel by the JTAG logic.

  • Page 227: Once Port Capabilities, Once Port Architecture

    OnCE Port As emulation capabilities are necessarily tied to the particular implementation of a DSP56800-based device, the appropriate device’s user’s manual should be consulted for complete details on implementation and supported functions. 9.3.1 OnCE Port Capabilities The capabilities of the OnCE port include the following: •...

  • Page 228

    OnCE port module is handled via the JTAG port and thus may be considered the primary communications sub-module for the OnCE port, although it operates independently. The operations of the OnCE port occur independently of the main DSP56800 core logic, and require no core resources. DSP56800 Family Manual...

  • Page 229: Command, Status, And Control, Breakpoint And Trace, Pipeline Save And Restore, Fifo History Buffer

    JTAG port module, and are passed transparently through to this logic, which is responsible for coordinating all emulation and debugging activity. As previously noted, all emulation and debug processing takes place independently of the main DSP56800 processor core. This allows for instructions to be executed in debug mode at full speed, without any overhead introduced by the debugging logic.

  • Page 230

    JTAG and On-Chip Emulation (OnCE™) DSP56800 Family Manual...

  • Page 231: A.1 Notation, Table A-1 Register Fields For General-purpose Writes And Reads

    Also included is a section on instruction timing, which shows the number of program words and execution time of each instruction. Finally, the instruction set summary, which shows the syntax of all allowed DSP56800 instructions, is presented.

  • Page 232: Table A-2 Address Generation Unit (agu) Registers, Table A-3 Data Alu Registers

    Address operands used in the instruction field sections of the instruction descriptions are given in Table A-4. Addressing mode operators that are accepted by the assembler for specifying a specific addressing mode are shown in Table A-5. DSP56800 Family Manual...

  • Page 233: Table A-4 Address Operands, Table A-5 Addressing Mode Operators, Table A-6 Miscellaneous Operands

    Table A-4. Address Operands Symbol Description Effective address Effective address for X bus xxxx Absolute address (16 bits) I/O short address (6 bits, one-extended) Absolute address (6 bits, zero-extended) <...> Specifies the contents of the specified address X memory reference Program memory reference Table A-5.

  • Page 234: Table A-7 Other Symbols

    Most significant word Rounding constant Limiting when reading a data ALU accumulator <op> Generic instruction (specifically defined within each section) For instruction names that contain parentheses, such as DEC(W) or IMPY(16), the portion within the parentheses is optional. DSP56800 Family Manual...

  • Page 235: A.2 Programming Model

    Programming Model The registers in the DSP56800 core programming model are shown in Figure A-1. Data Arithmetic Logic Unit Data ALU Input Registers 16 15 Accumulator Registers 16 15 16 15 Address Generation Unit Pointer Offset Modifier Registers Register Register...

  • Page 236: A.3 Addressing Modes, A.4 Condition Code Computation

    The CC bit specifies whether condition codes are generated using the information in the extension register. See Section A.4.2, “Effects of the Operating Mode Register’s SA Bit,” and Section A.4.3, “Effects of the OMR’s CC Bit,” for more information. DSP56800 Family Manual...

  • Page 237: A.4.1 The Condition Code Bits, A.4.1.1 Size (sz)—bit 7

    A.4.1 The Condition Code Bits The DSP56800 family defines eight condition code bits, which are contained in the lower-order 8 bits of the Status Register (SR) as follows: Status Register Reset = $0300 Read/Write LF—Loop Flag I1,I0—Interrupt Mask SZ—Size L—Limit E—Extension...

  • Page 238: A.4.1.2 Limit (l)—bit 6, A.4.1.3 Extension In Use (e)—bit 5

    32 bits. E is cleared if all of the upper 5 bits of the result are 00000 or 11111 and is set otherwise. E is not affected by the OMR’s CC bit. DSP56800 Family Manual...

  • Page 239: A.4.1.4 Unnormalized (u)—bit 4, A.4.1.5 Negative (n)—bit 3

    NOTE: When the SA bit in the OMR register is set to one, the E bit is set based on the result before passing through the MAC Output Limiter. If SA is set to one and saturation does occur in the MAC Output Limiter, this can result in the E bit being set, even though the result is saturated to a value where the extension portion is not in use.

  • Page 240: A.4.1.6 Zero (z)—bit 2, A.4.1.7 Overflow (v)—bit 1, A.4.1.8 Carry (c)—bit 0

    For 20- or 36-bit results, the carry or borrow is generated out of bit 35. For 32-bit results, the carry or borrow is generated out of bit 31. The carry or borrow is generated out of bit 15 for 16-bit results. C is not affected by the OMR’s CC or SA bits. A-10 DSP56800 Family Manual...

  • Page 241: A.4.2 Effects Of The Operating Mode Register's Sa Bit

    A.4.2 Effects of the Operating Mode Register’s SA Bit The SA bit in the Operating Mode Register (OMR) can affect the computation of certain condition code bits. This bit enables the MAC Output Limiter within the data ALU. When enabled, the results of many operations are limited to fit with 32 bits, the extension portion containing only sign information.

  • Page 242: A.4.4 Condition Code Summary By Instruction

    For example, the Z flag computation for the CLR instruction is shown as the standard definition, while the opcode description indicates that the Z flag is always set. Table A-9 gives the chip implementation viewpoint, while the opcode descriptions give the user viewpoint. A-12 DSP56800 Family Manual...

  • Page 243: Table A-9 Condition Code Summary

    The “Comments” column in the table is also used to report if any of the upper bits in the status register are modified. These are not status bits because they do not lie in the status portion of the status register, but rather in the control portion.

  • Page 244

    V cleared MPYSU — — V cleared — — — — — — — — NORM — — — — — — — — — — — — — — — — — — — — A-14 DSP56800 Family Manual...

  • Page 245

    Table A-9. Condition Code Summary (Continued) Instruction Comments — — — — — — — — — — — — — — — — Restored — (9) — — — — — — — — — STOP — — — —...

  • Page 246: A.5 Instruction Timing

    Instruction Timing This section describes how to calculate the DSP56800 instruction timing manually using the provided tables. Three complete examples are presented to illustrate the use of the tables. Alternatively, the user can obtain the number of instruction program words and the number of oscillator clock cycles required for a given instruction by using the simulator;...

  • Page 247: Table A-10 Instruction Timing Symbols

    • Table A-14 on page A-20 gives the number of additional (if any) clock cycles for each type of MOVEM operation. • Table A-15 on page A-20 gives the number of additional (if any) clock cycles for each type of bit-field manipulation (BFCHG, BFCLR, BFSET, BFTSTH, BFTSTL, BRCLR, and BRSET) operation.

  • Page 248: Table A-11 Instruction Timing Summary

    BFCLR 2+ea 4+mvb MPYR 2+mv BFSET 2+ea 4+mvb MPYSU BFTSTH 2+ea 4+mvb 2+mv BFTSTL 2+ea 4+mvb 6+jx NORM BRCLR 2+ea 8+mvb+jx BRSET 2+ea 8+mvb+jx NOTC 2+ea 4+mvb 2+mv 1+mva 2+(ea or mv) 2+ea 4+mvb DEBUG 2+ea A-18 DSP56800 Family Manual...

  • Page 249: Table A-12 Parallel Move Timing

    Table A-11. Instruction Timing Summary (Continued) Instruction Instruction Mnemonic Clock Cycles Mnemonic Clock Cycles Words Words DEC(W) 1+ea 2+(ea or mv) 2+mv ENDDO 10+rx EORC 2+ea 4+mvb 10+rx ILLEGAL IMPY(16) STOP INC(W) 1+ea 2+(ea or mv) 1+ea 2+(ea or mv) 4+jx 6+jx 8+jx...

  • Page 250: Table A-13 Movec Timing Summary, Table A-14 Movem Timing Summary

    + 1. If the jump instruction was fetched from a program memory segment with wait states, another “ap” should be added to account for that third fetch. A-20 DSP56800 Family Manual...

  • Page 251: Table A-17 Rts Timing Summary, Table A-18 Tstw Timing Summary

    Table A-17. RTS Timing Summary Operation +rx Cycles RTI, RTS 2 * ap + 2 * ax NOTE: The term “2 * ap” represents the two instruction fetches done by the RTI/RTS instruction to refill the pipeline. The ax term represents fetching the return address from the software stack when the stack pointer points to external X memory, and the 2 * ax term includes both this fetch and the fetch of the SR as performed by the RTI and RTS instructions.

  • Page 252: Table A-20 Memory Access Timing Summary

    P memory access wait states Three examples using the preceding tables follow. Example A-1. Arithmetic Instruction with Two Parallel Reads Problem Calculate the number of DSP56800 instruction program words and the number of oscillator clock cycles required for the following instruction: MACR X0,Y0,A X:(R0)+,Y0...

  • Page 253

    A-20, or Table A-15 on page A-20, respectively. Example A-2. Jump Instruction Problem Calculate the number of DSP56800 instruction program words and the number of oscillator clock cycles required for the following instruction: JEQ $2000 Where the following conditions are true: •...

  • Page 254

    (1 + 1) = (1 + 1) = 2 instruction program word and will execute in (4 + jx) = (4 + ea + (2 * ap)) = (4 + ea + (2 * wp)) = (4 + 2 + (2 * 4)) = 14 oscillator clock cycles. A-24 DSP56800 Family Manual...

  • Page 255

    Example A-3. RTS Instruction Problem Calculate the number of DSP56800 instruction program words and the number of oscillator clock cycles required for the following instruction: Where the following conditions are true: • OMR = $02 (normal expanded memory map). •...

  • Page 256: A.6 Instruction Set Restrictions

    Instruction Set Restrictions These items are restrictions on the DSP56800 instruction set: • A NORM instruction cannot be immediately followed by an instruction that accesses X memory using the R0 pointer. In addition, NORM can only use the R0 address register.

  • Page 257: A.7 Instruction Descriptions

    Instruction Descriptions This section describes in complete detail each instruction in the DSP56800 Family instruction set. The format of each instruction description is given in Section A.1, “Notation,” at the beginning of this appendix. Instructions that allow parallel moves include the notation “(parallel move)” in both the “Assembler Syntax”...

  • Page 258

    — Set according to the standard definition of the U bit — Set if bit 35 of A or B result is set except during saturation. — Set if A or B result equals zero — Set if overflow has occurred in A or B result A-28 DSP56800 Family Manual...

  • Page 259

    Absolute Value Instruction Fields: Operation Operands Comments Absolute value. Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination X:(Rn)+ X:(Rn)+N Timing: 2 + mv oscillator clock cycles Memory: 1 program word Instruction Set Details A-29...

  • Page 260

    C is set correctly for multi-precision arithmetic, using long word operands only when the extension register of the destination accumulator (A2 or B2) contains sign extension of bit 31 of the destination accumulator (A or B). A-30 DSP56800 Family Manual...

  • Page 261

    Add Long with Carry Condition Codes Affected: — Set if overflow has occurred in result — Set if the signed integer portion of A or B result is in use — Set according to the standard definition of the U bit —...

  • Page 262

    C is set correctly using word or long word source operands if the extension register of the destination accumulator (A2 or B2) contains sign extension from bit 31 of the destination accumulator (A or B). C is always set correctly by using accumulator source operands. A-32 DSP56800 Family Manual...

  • Page 263

    Condition Codes Affected: SZ — Set according to the standard definition of the S bit (parallel move) — Set if limiting (parallel move) or overflow has occurred in result — Set if the signed integer portion of A or B result is in use —...

  • Page 264

    Refer to previous tables for ADD instructions without a parallel move. Memory: 1 program word for ADD instructions with a single or dual parallel move. Refer to previous tables for ADD instructions without a parallel move. A-34 DSP56800 Family Manual...

  • Page 265

    Logical AND Operation: Assembler Syntax: S • D → D (no parallel move) (no parallel move) S • D[31:16] → D[31:16] (no parallel move) (no parallel move) where • denotes the logical AND operator Description: Logically AND the source operand (S) with the destination operand (D) and store the result in the des- tination.

  • Page 266

    For other destination operands: — Set if data limiting occurred during 36-bit source move — Set if all bits specified by the mask are set Clear if not all bits specified by the mask are set A-36 DSP56800 Family Manual...

  • Page 267

    ANDC ANDC Logical AND, Immediate Instruction Fields: Operation Operands Comments BFCLR #xxxx,DDDDD Absolute value. All registers in DDDDD are permitted except HWS. #xxxx,X:(R2+xx) X:aa represents a 6-bit absolute address. Refer to #xxxx,X:(SP-xx) Absolute Short Address (Direct Addressing): <aa> on page 4-22. #xxxx,X:aa X:pp represents a 6-bit absolute I/O address.

  • Page 268

    The U bit of CCR (bit 4) is set because the result is not normalized, the E bit of CCR (bit 5) is set because the signed integer portion of the result is in use, and the L bit of CCR (bit 6) is set because an overflow has occurred. A-38 DSP56800 Family Manual...

  • Page 269

    Arithmetic Shift Left Condition Codes Affected: SZ — Set according to the standard definition of the S bit (parallel move) — Set if limiting (parallel move) or overflow has occurred in result — Set if the signed integer portion of A or B result is in use —...

  • Page 270

    — Set if bit 35 of A or B result is set except during saturation — Set if A or B result equals zero Note: If the CC bit is set, N is undefined and Z is set if the LSBs 31–0 are zero. A-40 DSP56800 Family Manual...

  • Page 271

    ASLL ASLL Multi-Bit Arithmetic Left Shift Instruction Fields: Operation Operands Comments ASLL Y1,X0,FDD Arithmetic shift left of the first operand by value Y0,X0,FDD specified in four LSBs of the second operand; Y1,Y0,FDD places result in FDD Y0,Y0,FDD A1,Y0,FDD B1,Y1,FDD Timing: 2 oscillator clock cycles Memory: 1 program word...

  • Page 272

    The N bit of CCR (bit 3) is also set because bit 35 of the result in A is set. The E bit of CCR (bit 5) is set because the signed integer portion of B is used by the result. A-42 DSP56800 Family Manual...

  • Page 273

    Arithmetic Shift Right Condition Codes Affected: SZ — Set according to the standard definition of the S bit (parallel move) — Set if data limiting has occurred during parallel move — Set if the signed integer portion of A or B result is in use —...

  • Page 274

    — Set if A or B result equals zero See Section 3.6.2, “36-Bit Destinations—CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Desti- nations—CC Bit Set,” on page 3-34 for the case when the CC bit is set. A-44 DSP56800 Family Manual...

  • Page 275

    ASRAC ASRAC Arithmetic Right Shift with Accumulate Instruction Fields: Operation Operands Comments ASRAC Y1,X0,F Arithmetic word shifting with accumulation Y0,X0,F Y1,Y0,F Y0,Y0,F A1,Y0,F B1,Y1,F Timing: 2 oscillator clock cycles Memory: 1 program word Instruction Set Details A-45...

  • Page 276

    Since the destination is an accumulator, the extension word (A2) is filled with sign extension, and the LSP (A0) is set to zero. Condition Codes Affected: — Set if bit 35 of A or B result is set except during saturation — Set if A or B result equals zero A-46 DSP56800 Family Manual...

  • Page 277

    ASRR ASRR Multi-Bit Arithmetic Right Shift Instruction Fields: Operation Operands Comments ASRR Y1,X0,FDD Arithmetic shift right of the first operand by value Y0,X0,FDD specified in four LSBs of the second operand; Y1,Y0,FDD places result in FDD Y0,Y0,FDD A1,Y0,FDD B1,Y1,FDD Timing: 2 oscillator clock cycles Memory: 1 program word...

  • Page 278

    INCW instruction. The Bcc instruction uses a PC-relative offset of two for this example. Restrictions: A Bcc instruction used within a DO loop cannot begin at the LA or LA-1 within that DO loop. A Bcc instruction cannot be repeated using the REP instruction. A-48 DSP56800 Family Manual...

  • Page 279

    Branch Conditionally Condition Codes Affected: The condition codes are tested but not modified by this instruction. Instruction Fields: Operation Operands Comments <OFFSET7> 7-bit signed PC relative offset Timing: 4 + jx oscillator clock cycles Memory: 1 program word Instruction Set Details A-49...

  • Page 280

    — Set if all bits specified by the mask are set Clear if not all bits specified by the mask are set Note: If all bits in the mask are set to zero, the destination is unchanged, and the C bit is set. A-50 DSP56800 Family Manual...

  • Page 281

    BFCHG BFCHG Test Bit Field and Change Instruction Fields: Operation Operands Comments BFCHG #xxxx,DDDDD BFCHG tests all bits selected by the 16-bit immedi- ate mask. If all selected bits are set, then the C bit is #xxxx,X:(R2+xx) set. Otherwise it is cleared. Then it inverts all selected bits.

  • Page 282

    — Set if all bits specified by the mask are set Clear if not all bits specified by the mask are set Note: If all bits in the mask are set to zero, the destination is unchanged, and the C bit is set. A-52 DSP56800 Family Manual...

  • Page 283

    BFCLR BFCLR Test Bit Field and Clear Instruction Fields: Operation Operands Comments BFCLR #xxxx,DDDDD BFCLR tests all bits selected by the 16-bit immedi- ate mask. If all selected bits are set, then the C bit is #xxxx,X:(R2+xx) set. Otherwise it is cleared. Then it clears all selected bits.

  • Page 284

    — Set if all bits specified by the mask are set Clear if not all bits specified by the mask are set Note: If all bits in the mask are set to zero, the destination is unchanged, and the C bit is set. A-54 DSP56800 Family Manual...

  • Page 285

    BFSET BFSET Test Bit Field and Set Instruction Fields: Operation Operands Comments BFSET #xxxx,DDDDD BFSET tests all bits selected by the 16-bit immedi- ate mask. If all selected bits are clear, then the C bit #xxxx,X:(R2+xx) is set. Otherwise it is cleared. Then it sets all selected bits.

  • Page 286

    — Set if all bits specified by the mask are set Clear if not all bits specified by the mask are set Note: If all bits in the mask are set to zero, the destination is unchanged, and the C bit is set. A-56 DSP56800 Family Manual...

  • Page 287

    BFTSTH BFTSTH Test Bit Field High Instruction Fields: Operation Operands Comments BFTSTH #xxxx,DDDDD BFTSTH tests all bits selected by the 16-bit immedi- ate mask. If all selected bits are set, then the C bit is #xxxx,X:(R2+xx) set. Otherwise it is cleared. #xxxx,X:(SP-xx) All registers in DDDDD are permitted except HWS.

  • Page 288

    #xxxx,X:pp X:pp represents a 6-bit absolute I/O address. Refer to I/O Short Address (Direct Addressing): <pp> #xxxx,X:xxxx on page 4-23. Timing: Refer to the preceding Instruction Fields table Memory: Refer to the preceding Instruction Fields table A-58 DSP56800 Family Manual...

  • Page 289

    Branch Operation: Assembler Syntax: PC+label → PC <OFFSET7> Description: Branch to the location in program memory at PC + displacement. The PC contains the address of the next instruction. The displacement is a 7-bit signed value that is sign extended to form the PC-relative offset.

  • Page 290

    — Set if all bits specified by the mask are cleared Clear if not all bits specified by the mask are cleared Note: If all bits in the mask are set to zero, C is set, and the branch is taken. A-60 DSP56800 Family Manual...

  • Page 291

    BRCLR BRCLR Branch if Bits Clear Instruction Fields: Operation Operands Comments BRCLR #MASK8,DDDDD,AA 10/8 BRCLR tests all bits selected by the immediate mask. If all selected bits are clear, then the carry #MASK8,X:(R2+xx),AA 12/10 bit is set and a PC relative branch occurs. Other- wise it is cleared and no branch occurs.

  • Page 292

    — Set if all bits specified by the mask are set Clear if not all bits specified by the mask are set Note: If all bits in the mask are set to zero, C is set and the branch is taken. A-62 DSP56800 Family Manual...

  • Page 293

    BRSET BRSET Branch if Bits Set Instruction Fields: Operation Operands Comments BRSET #MASK8,DDDDD,AA 10/8 BRSET tests all bits selected by the immediate mask. If all selected bits are set, then the carry bit #MASK8,X:(R2+xx),AA 12/10 is set and a PC relative branch occurs. Otherwise it is cleared and no branch occurs.

  • Page 294

    — Always set if destination is a 36-bit accumulator — Always cleared if destination is a 36-bit accumulator Note: The condition codes are only affected if the destination of the CLR instruction is one of the two 36-bit accumulators (A or B). A-64 DSP56800 Family Manual...

  • Page 295

    Clear Accumulator Instruction Fields: Operation Operands Comments Clear 36-bit accumulator and set condition codes. F1DD Identical to move #0,<reg>; does not set condition codes. Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination X:(Rn)+ X:(Rn)+N Timing: 2 + mv oscillator clock cycles...

  • Page 296

    16-bit value in the Y0 register with 16 LS zeros, sign extends the resulting 32-bit long word to 36 bits, subtracts the result from the 36-bit A accumulator, and updates the CCR (leaving the A accumulator unchanged). A-66 DSP56800 Family Manual...

  • Page 297

    Compare Condition Codes Affected: SZ — Set according to the standard definition of the SZ bit (parallel move) — Set if limiting (parallel move) or overflow has occurred in result — Set if the signed integer portion of the result is in use —...

  • Page 298

    OnCE commands. If this bit is not clear, then the processor simply executes two NOPs and continues program execution. Condition Codes Affected: No condition codes are affected. Instruction Fields: Operation Operands Comments DEBUG Generate a debug event Timing: 4 oscillator clock cycles Memory: 1 program word A-68 DSP56800 Family Manual...

  • Page 299

    DEC(W) DEC(W) Decrement Word Operation: Assembler Syntax: D2:D1-1 → D2:D1 (parallel move) DECW (parallel move) Description: Decrement a 16-bit destination or the two upper portions (A2:A1 or B2:B1) of a 36-bit accumulator. If the destination is a 36-bit accumulator, leave the LSP (A0 or B0) unchanged. Usage: This instruction is typically used when processing integer data.

  • Page 300

    Decrement Word Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination DEC(W) X:(Rn)+ X:(Rn)+N Timing: Refer to the preceding Instruction Fields table Memory: Refer to the preceding Instruction Fields table A-70 DSP56800 Family Manual...

  • Page 301

    Divide Iteration Operation: Assembler Syntax: (see following figure) (no parallel move) D[35] ⊕ S[15] = 1 Then D1 + S Else D1 - S Description: This instruction is a divide iteration used to calculate 1 bit of the result of a division. After the correct number of iterations, this will divide the destination operand (D)—dividend or numerator—by the source operand (S)—divisor or denominator—and store the result in the destination accumulator.

  • Page 302

    — Set if the MSB of the destination operand is changed as a result of the instruction’s left shift operation — Set if bit 35 of the result is cleared Instruction Fields: Operation Operands Comments DD,F Divide iteration Timing: 2 oscillator clock cycles Memory: 1 program word A-72 DSP56800 Family Manual...

  • Page 303

    Start Hardware Do Loop Operation upon Executing DO Instruction: Assembler Syntax: HWS[0] → HWS[1]; #xx → LC #xx,expr PC → HWS[0]; LF → NL; expr → LA 1 → LF HWS[0] → HWS[1]; S → LC S,expr PC → HWS[0]; LF → NL; expr → LA 1 →...

  • Page 304

    If LC is zero upon entering the DO loop, the loop is executed 2 times. To avoid this, use the software technique outlined in Section 8.6, “Loops,” on page 8-20. Condition Codes Affected: LF — Set when a DO loop is in progress — Set if data limiting occurred A-74 DSP56800 Family Manual...

  • Page 305

    Start Hardware Do Loop Restrictions: The end-of-loop comparison previously described occurs at instruction fetch time. That is, LA is com- pared with PC when the instruction at the LA-2 is being executed. Therefore, instructions that access the program controller registers or change program flow cannot be used in locations LA-2, LA-1, or Proper DO loop operation is not guaranteed if an instruction starting at the LA-2, LA-1, or LA specifies one of the program controller registers SR, SP, LA, LC, or (implicitly) PC as a destination register.

  • Page 306

    Otherwise, skip body of loop (adds three additional cycles). The last address is 16-bit absolute. Any register allowed except: SP, M01, SR, OMR, and HWS. Timing: 6 oscillator clock cycles Memory: 2 program words A-76 DSP56800 Family Manual...

  • Page 307

    ENDDO ENDDO End Current DO Loop Operation: Assembler Syntax: NL → LF ENDDO HWS[1] → HWS[0]; 0 → NL Description: Terminate the current hardware DO loop immediately. Normally, a hardware DO loop is terminated when the last instruction of the loop is executed and the current LC equals one, but this instruction can terminate a loop before normal completion.

  • Page 308

    Comments ENDDO Remove one value from the hardware stack and update the NL and LF bits appropriately Note: Does not branch to the end of the loop Timing: 2 oscillator clock cycles Memory: 1 program word A-78 DSP56800 Family Manual...

  • Page 309

    Logical Exclusive OR Operation: Assembler Syntax: S ⊕ D → D (no parallel move) (no parallel move) S ⊕ D[31:16] → D[31:16] (no parallel move) (no parallel move) where ⊕ denotes the logical exclusive OR operator Description: Logically exclusive OR the source operand (S) with the destination operand (D) and store the result in the destination.

  • Page 310

    Logical Exclusive OR Instruction Fields: Operation Operands Comments DD,FDD 16-bit exclusive OR (XOR) F1,DD Timing: 2 oscillator clock cycles Memory: 1 program word A-80 DSP56800 Family Manual...

  • Page 311

    EORC EORC Logical Exclusive OR Immediate Operation: Assembler Syntax: #xxxx ⊕ X:<ea> → X:<ea> EORC #iiii,X:<ea> #xxxx ⊕ D → D EORC #iiii,D where ⊕ denotes the logical exclusive OR operator Implementation Note: This instruction is an alias to the BFCHG instruction, and assembles as BFCHG with the 16-bit imme- diate value as the bit mask.

  • Page 312

    #xxxx,X:pp X:pp represents a 6-bit absolute I/O address. Refer to I/O Short Address (Direct Addressing): <pp> #xxxx,X:xxxx on page 4-23. Timing: Refer to the preceding Instruction Fields table Memory: Refer to the preceding Instruction Fields table A-82 DSP56800 Family Manual...

  • Page 313

    ILLEGAL ILLEGAL Illegal Instruction Interrupt Operation: Assembler Syntax: Begin illegal instruction exception routine ILLEGAL (no parallel move) Description: Normal instruction execution is suspended and illegal instruction exception processing is initiated. The interrupt priority level bits (I1 and I0) are set to 11 in the status register. The purpose of the illegal in- terrupt is to force the DSP into an illegal instruction exception for test purposes.

  • Page 314

    ($0003 and $0004). The contents of the destination accumulator are not important prior to ex- ecution. Execution of the IMPY X0,Y0,A instruction integer multiplies X0 and Y0 and stores the re- sult ($000C) in A1. A0 remains unchanged, and A2 is sign extended. A-84 DSP56800 Family Manual...

  • Page 315

    IMPY(16) IMPY(16) Integer Multiply Condition Codes Affected: — Not defined — Not defined — Set if bit 35 of the result is set except during saturation — Set if the 20 MSBs of the result equal zero — Set if overflow occurs in the 16-bit result Instruction Fields: Operation Operands...

  • Page 316

    See Section 3.6.5, “16-Bit Destinations,” on page 3-35 for cases with X0, Y0, or Y1 as D. See Section 3.6.2, “36-Bit Destinations—CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Desti- nations—CC Bit Set,” on page 3-34 for the case when the CC bit is set. A-86 DSP56800 Family Manual...

  • Page 317

    INC(W) INC(W) Increment Word Instruction Fields: Operation Operands Comments INC(W) Increment word X:(SP-xx) Increment word in memory using appropriate addressing mode. X:aa X:aa represents a 6-bit absolute address. Refer to X:xxxx Absolute Short Address (Direct Addressing): <aa> on page 4-22. Data ALU Operation Parallel Memory Read or Write Operation...

  • Page 318

    INCW instruction. The Jcc instruction uses a 16-bit absolute address for this example. Restrictions: A Jcc instruction used within a DO loop cannot begin at the LA or LA-1 within that DO loop. A Jcc instruction cannot be repeated using the REP instruction. A-88 DSP56800 Family Manual...

  • Page 319

    Jump Conditionally Condition Codes Affected: The condition codes are tested but not modified by this instruction. Instruction Fields: Operation Operands Comments xxxx 16-bit absolute address Timing: 4 + jx oscillator clock cycles Memory: 2 program words Instruction Set Details A-89...

  • Page 320

    A JMP instruction used within a DO loop cannot begin at the LA within that DO loop. A JMP instruction cannot be repeated using the REP instruction. Instruction Fields: Operation Operands Comments xxxx 16-bit absolute address Timing: 6 + jx oscillator clock cycle Memory: 2 program words A-90 DSP56800 Family Manual...

  • Page 321

    Jump to Subroutine Operation: Assembler Syntax: → SP SP+1 xxxx → X:(SP) → SP SP+1 → X:(SP) → PC xxxx Description: Jump to subroutine in program memory at the location given by the instruction’s effective address. The effective address is a 16-bit absolute address. Example: LABEL ;...

  • Page 322

    (SP-xx) Subtract a 6-bit unsigned immediate value from SP and store in the SP register (Rn+xxxx) Add a 16-bit signed immediate value to the specified source register. Timing: 2+ea oscillator clock cycles Memory: 1+ea program words A-92 DSP56800 Family Manual...

  • Page 323

    Logical Shift Left Operation: Assembler Syntax: (see following figure) Unch. Unchanged (no parallel move) Description: Logically shift 16 bits of the destination operand (D) 1 bit to the left and store the result in the desti- nation. If the destination is a 36-bit accumulator, the result is stored in the MSP of the accumulator (A1 or B1), and the remaining portions of the accumulator (A2, B2, A0, B0) are not modified.

  • Page 324

    — Set if bit 31 of A or B was set prior to the execution of the instruction Instruction Fields: Operation Operands Comments 1-bit logical shift left of word Timing: 2 oscillator clock cycles Memory: 1 program word A-94 DSP56800 Family Manual...

  • Page 325

    LSLL LSLL Multi-Bit Logical Left Shift Operation: Assembler Syntax: S1 << S2 → D (no parallel move) LSLL S1,S2,D (no parallel move) Description: Logically shift the first 16-bit source operand (S1) to the left by the value contained in the lowest 4 bits of the second source operand (S2) and store the result in the destination register (D).

  • Page 326

    Logical shift left of the first operand by value speci- Y0,X0,FDD fied in four LSBs of the second operand; places Y1,Y0,FDD result in FDD Y0,Y0,FDD A1,Y0,FDD Implemented using ASLL instruction B1,Y1,FDD Timing: 2 oscillator clock cycles Memory: 1 program word A-96 DSP56800 Family Manual...

  • Page 327

    Logical Shift Right Operation: Assembler Syntax: (see following figure) (no parallel move) Unch. Unchanged Description: Logically shift 16 bits of the destination operand (D) 1 bit to the right and store the result in the desti- nation. If the destination is a 36-bit accumulator, the result is stored in the MSP of the accumulator (A1 or B1), and the remaining portions of the accumulator (A2, B2, A0, B0) are not modified.The LSB of the destination (bit 16 if the destination is a 36-bit accumulator) prior to the execution of the instruction is shifted into C, and zero is shifted into the MSB of D1 (bit 31if the destination is a 36-bit accumula-...

  • Page 328

    — Set if bit 16 of A or B was set prior to the execution of the instruction Instruction Fields: Operation Operands Comments 1-bit logical shift right of word Timing: 2 oscillator clock cycles Memory: 1 program word A-98 DSP56800 Family Manual...

  • Page 329

    LSRAC LSRAC Logical Right Shift with Accumulate Operation: Assembler Syntax: S1 >> S2 + D → D (no parallel move) LSRAC S1,S2,D (no parallel move) Description: Logically shift the first 16-bit source operand (S1) to the right by the value contained in the lowest 4 bits of the second source operand (S2), and accumulate the result with the value in the destination reg- ister (D).

  • Page 330

    LSRAC LSRAC Logical Right Shift with Accumulate Instruction Fields: Operation Operands Comments LSRAC Y1,X0,F Logical word shifting with accumulation Y0,X0,F Y1,Y0,F Y0,Y0,F A1,Y0,F B1,Y1,F Timing: 2 oscillator clock cycles Memory: 1 program word A-100 DSP56800 Family Manual...

  • Page 331

    LSRR LSRR Multi-Bit Logical Right Shift Operation: Assembler Syntax: S1 >> S2 → D (no parallel move) LSRR S1,S2,D (no parallel move) Description: Logically shift the first 16-bit source operand (S1) to the right by the value contained in the lowest 4 bits of the second source operand (S2), and store the result in the destination register (D).

  • Page 332

    LSBs of the second operand; places Y1,Y0,FDD result in FDD (when result is to an accumulator F, Y0,Y0,FDD zero extends into F2) A1,Y0,FDD B1,Y1,FDD Timing: 2 oscillator clock cycles Memory: 1 program word A-102 DSP56800 Family Manual...

  • Page 333

    Multiply-Accumulate Operation: Assembler Syntax: D + S1 * S2 → D (no parallel move) (+)S1,S2,D (no parallel move) D + S1 * S2 → D (one parallel move) S1,S2,D (one parallel move) D + S1 * S2 → D (two parallel reads) S1,S2,D (two parallel reads) Description: Multiply the two signed 16-bit source operands (S1 and S2) and add or subtract the product to or from...

  • Page 334

    2 + mv oscillator clock cycles for MAC instructions with a parallel move Refer to previous table for MAC instructions without a parallel move Memory: 1 program word for MAC instructions with a parallel move Refer to previous table for MAC instructions without a parallel move A-104 DSP56800 Family Manual...

  • Page 335

    MACR MACR Multiply-Accumulate and Round Operation: Assembler Syntax: D + S1 * S2 + r → D (no parallel move) MACR (+)S1,S2,D(no parallel move) D + S1 * S2 + r → D (one parallel move) MACR S1,S2,D (one parallel move) D + S1 * S2 + r →...

  • Page 336

    (±)Y1,Y0,FDD (±)Y0,Y0,FDD (±)A1,Y0,FDD (±)B1,Y1,FDD Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination MACR Y1,B1,F X:(Rn)+ Y0,Y0,F X:(Rn)+N Y0,A1,F X0,Y0,F X0,Y1,F Y0,Y1,F (F = A or B) A-106 DSP56800 Family Manual...

  • Page 337

    MACR MACR Multiply-Accumulate and Round Data ALU First and Second Memory Destinations for Memory Operation Reads Reads Operation Registers Read1 Read2 Destination1 Destination2 MACR Y0,X0,F X:(R0)+ X:(R3)+ Y1,X0,F X:(R0)+N X:(R3)- Y1,Y0,F X:(R1)+ Valid Valid (F = A or B) X:(R1)+N destinations destinations for Read1...

  • Page 338

    A accumulator. If this were a MAC instruction, Y0 ($8000) would equal -1.0, and the multiplication result would be $F:CBAA:0000. Since this is a MACSU instruction, Y0 is consid- ered unsigned and equals +1.0. This gives a multiplication result of $0:3456:0000. A-108 DSP56800 Family Manual...

  • Page 339

    MACSU MACSU Multiply-Accumulate Signed × Unsigned Condition Codes Affected: — Set if the signed integer portion of A or B result is in use — Set according to the standard definition of the U bit — Set if bit 35 of A or B result is set except during saturation —...

  • Page 340

    MOVE Introduction to DSP56800 Moves Description: The DSP56800 Family instruction set contains a powerful set of moves, resulting not only in better DSP performance, but in simpler, more efficient general-purpose computing. The powerful set of con- troller and DSP moves results not only in ease of programming, but in more efficient code that, in turn, results in reduced power consumption for an application.

  • Page 341

    Description: Two types of parallel moves are permitted—register-to-memory moves and dual memory-to-register moves. Both types of parallel moves use a restricted subset of all available DSP56800 addressing modes, and the registers available for the move portion of the instruction are also a subset of the total set of DSP core registers.

  • Page 342

    TST, CMP, and CMPM allow both the accumulator and its lower portion (A and A0, B and B0) to be the parallel move destination even if this accumulator is used by the data ALU operation. These in- structions do not have a true destination. A-112 DSP56800 Family Manual...

  • Page 343

    MOVE MOVE Parallel Move—Single Parallel Move Example: A,X:(R3)+N ; save old value of A in X:(R3), ; A*2 → A, update R3 Before Execution After Execution 5555 3333 AAAA CCCC X:$00FF X:$00FF 1234 5555 00FF 0103 0004 0004 Explanation of Example: Prior to execution, the 16-bit R3 address register contains the value $00FF, the A accumulator contains the value $0:5555:3333, and the 16-bit X memory location X:$00FF contains the value $1234.

  • Page 344

    X0 and Y0, and the result is convergently rounded before storing it in the accumulator. Note: The second X data memory parallel read using the R3 address register can never access off-chip mem- ory or on-chip peripherals. It can only access on-chip X data memory. A-114 DSP56800 Family Manual...

  • Page 345

    MOVE MOVE Parallel Move—Dual Parallel Reads Condition Codes Affected: — Set if data limiting has occurred during parallel move Instruction Fields: Data ALU First and Second Memory Destinations for Memory Operation Reads Reads Operation Registers Read1 Read2 Destination1 Destination2 Operation Operands X:(R0)+ X:(R3)+...

  • Page 346

    N is not used, then the instruction is not stretched an additional cycle. If the N address register is changed with a bit-field instruction, the new contents will not be available for use until the second following instruction. A-116 DSP56800 Family Manual...

  • Page 347

    MOVE(C) MOVE(C) Move Control Register Example: MOVE(C) LC,X0 ; move the LC register into the X0 register Before Execution After Execution 0100 0100 0123 0100 Explanation of Example: Execution of the MOVE(C) instruction moves the contents of the program controller’s 16-bit LC reg- ister into the data ALU’s 16-bit X0 register.

  • Page 348

    — Set according to bit 1 of the source operand — Set according to bit 0 of the source operand If D1 and D2 are not SR: — Set if data limiting has occurred during move A-118 DSP56800 Family Manual...

  • Page 349

    MOVE(C) MOVE(C) Move Control Register Instruction Fields: Source or Source or Operation Comments Destination Destination MOVE(C) X:(Rn) Any register — X:(Rn)+ X:(Rn)- X:(Rn)+N X:(SP) X:(SP)+ X:(SP)- X:(SP)+N X:xxxx Any register 16-bit absolute address X:(Rn+N) Any register — X:(SP+N) X:(Rn+xxxx) Any register Signed 16-bit X:(SP+xxxx) index...

  • Page 350

    The MOVE(P) and MOVE(S) instructions also provide a mechanism for loading 16-bit immediate val- ues directly into the last 64 and first 64 locations, respectively, in X data memory. Condition Codes Affected: The condition codes are not affected by this instruction. A-120 DSP56800 Family Manual...

  • Page 351

    MOVE(I) MOVE(I) Move Immediate Instruction Fields: Operation Source Destination Comments MOVE HHHH Signed 7-bit integer data (data is put in the lowest 7 bits of the word portion of any MOVEI accumulator, upper 8 bits and extension reg are sign extended, LSP portion is set to “0”) #xxxx DDDDD...

  • Page 352

    $0077, the N register contains the value $0003, and the 16-bit program memory location P:(R2) con- tains the value $0116. Execution of the MOVE(M) instruction moves the 16-bit program memory lo- cation P:(R2) into the 36-bit A accumulator. R2 is then post-incremented by N. A-122 DSP56800 Family Manual...

  • Page 353

    MOVE(M) MOVE(M) Move Program Memory Condition Codes Affected: — Set if data limiting has occurred during the move Instruction Fields: Operation Source Destination Comments MOVE(M) P:(Rj)+ HHHH Read signed word from program P:(Rj)+N memory HHHH P:(Rj)+ Write word to program memory P:(Rj)+N Timing: 8 + mvm oscillator clock cycles...

  • Page 354

    This MOVE(P) instruction provides a more efficient way of accessing the last 64 locations in X mem- ory, which may be allocated to memory-mapped peripheral registers. Consult the specific DSP56800-based device’s user manual for information on where in the memory map peripheral regis- ters are located.

  • Page 355

    MOVE(P) MOVE(P) Move Peripheral Data Condition Codes Affected: — Set if data limiting has occurred during move Note: It is also possible to access the last 64 locations in the X data memory map using the MOVE(C) in- struction, which can directly access these locations either using the address-register-indirect address- ing modes or the absolute address addressing mode, which specifies a 16-bit absolute address.

  • Page 356

    Prior to execution, the contents of the X data memory location $0024 contains the value $AAAA. The MOVES zero-extends the value $24 to form the memory address $0024. Execution of the instruction moves the value $0342 into this location. A-126 DSP56800 Family Manual...

  • Page 357

    MOVE(S) MOVE(S) Move Absolute Short Condition Codes Affected: SZ — Set according to the standard definition of the SZ bit — Set if data limiting has occurred during move Note: It is also possible to access the first 64 locations in the X data memory using the MOVE(C) instruction, which can directly access these locations either using the address-register-indirect addressing modes or the absolute address addressing mode, which specifies a 16-bit absolute address.

  • Page 358

    See Section 3.6.5, “16-Bit Destinations,” on page 3-35 for cases with X0, Y0, or Y1 as D. See Section 3.6.2, “36-Bit Destinations—CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Desti- nations—CC Bit Set,” on page 3-34 for the case when the CC bit is set. A-128 DSP56800 Family Manual...

  • Page 359

    Signed Multiply Instruction Fields: Operation Operands Comments (±)Y1,X0,FDD Fractional multiply where one operand is optionally (±)Y0,X0,FDD negated before multiplication (±)Y1,Y0,FDD (±)Y0,Y0,FDD Note: Assembler also accepts first two operands (±)A1,Y0,FDD when they are specified in opposite order (±)B1,Y1,FDD Data ALU Operation Parallel Memory Read or Write Operation Registers...

  • Page 360

    See Section 3.6.5, “16-Bit Destinations,” on page 3-35 for cases with X0, Y0, or Y1 as D. See Section 3.6.2, “36-Bit Destinations—CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Desti- nations—CC Bit Set,” on page 3-34 for the case when the CC bit is set. A-130 DSP56800 Family Manual...

  • Page 361

    MPYR MPYR Signed Multiply and Round Instruction Fields: Operation Operands Comments MPYR (±)Y1,X0,FDD Fractional multiply where one operand is optionally (±)Y0,X0,FDD negated before multiplication; result is rounded (±)Y1,Y0,FDD (±)Y0,Y0,FDD Note: Assembler also accepts first two operands (±)A1,Y0,FDD when they are specified in opposite order (±)B1,Y1,FDD Data ALU Operation Parallel Memory Read or Write...

  • Page 362

    16-bit unsigned value in Y0 and stores the signed result into the A accumulator. If this was a MPY instruction, Y0 ($8000) would equal -1.0, and the multiplication result would be $F:CBAA:0000. Since this is a MPYSU instruction, Y0 is considered unsigned and equals +1.0. This gives a multiplication result of $0:3456:0000. A-132 DSP56800 Family Manual...

  • Page 363

    MPYSU MPYSU Signed Unsigned Multiply Condition Codes Affected: — Set if the signed integer portion of A or B result is in use — Set according to the standard definition of the U bit — Set if bit 35 of A or B result is set except during saturation —...

  • Page 364

    — Set if a borrow is generated from the MSB of the result See Section 3.6.2, “36-Bit Destinations—CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Desti- nations—CC Bit Set,” on page 3-34 for the case when the CC bit is set. A-134 DSP56800 Family Manual...

  • Page 365

    Negate Accumulator Instruction Fields: Operation Operands Comments Two’s-complement negation Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination X:(Rn)+ X:(Rn)+N Timing: 2 + mv oscillator clock cycles Memory: 1 program word Instruction Set Details A-135...

  • Page 366: No Operation Nop

    The NOP instruction increments the PC and completes any pending pipeline actions. Condition Codes Affected: The condition codes are not affected by this instruction. Instruction Fields: Operation Operands Comments No operation Timing: 2 oscillator clock cycles Memory: 1 program word A-136 DSP56800 Family Manual...

  • Page 367

    NORM NORM Normalize Accumulator Iteration Operation: Assembler Syntax: (E • U • Z = 1) NORM R0,D (no parallel move) ASL D and Rn - 1 → Rn then else if (E = 1) ASR D and Rn + 1 → Rn then else where X denotes the logical complement of X and...

  • Page 368

    Bit Set,” on page 3-34 for the case when the CC bit is set. Instruction Fields: Operation Operands Comments NORM R0,F Normalization iteration instruction for normalizing the F accumulator Timing: 2 oscillator clock cycles Memory: 1 program word A-138 DSP56800 Family Manual...

  • Page 369

    Logical Complement Operation: Assembler Syntax: D → D (no parallel move) (no parallel move) D[31:16] → D[31:16] (no parallel move) (no parallel move) where the bar over the D (D) denotes the logical NOT operator Description: Take the one’s-complement of the destination operand (D) and store the result in the destination. This instruction is a 16-bit operation.

  • Page 370

    R2. C is modified as described in following discussion. Condition Codes Affected: I0 SZ For destination operand SR: — Changed if specified in the field For other destination operands: — Set if the value equals $FFFF before the complement A-140 DSP56800 Family Manual...

  • Page 371

    NOTC NOTC Logical Complement with Carry Instruction Fields: Operation Operands Comments NOTC DDDDD One’s-complement (bit-wise negation). X:(R2+xx) All registers in DDDDD are permitted except HWS. X:(SP-xx) X:aa represents a 6-bit absolute address. Refer to Absolute Short Address (Direct Addressing): X:aa <aa>...

  • Page 372

    B1 and stores the 36-bit result in the B accumulator. Condition Codes Affected: I0 SZ — Set if bit 31 of A or B result is set — Set if bits 31–16 of A or B result are zero — Always cleared A-142 DSP56800 Family Manual...

  • Page 373

    Logical Inclusive OR Instruction Fields: Operation Operands Comments DD,FDD 16-bit logical OR F1,DD Timing: 2 oscillator clock cycles Memory: 1 program word Instruction Set Details A-143...

  • Page 374

    Condition Codes Affected: I0 SZ For destination operand SR: — Set as defined in the field and if specified in the field For other destination operands: — Set if all bits specified by the mask are set A-144 DSP56800 Family Manual...

  • Page 375

    Logical Inclusive OR Immediate Instruction Fields: Operation Operands Comments #xxxx,DDDDD 16-bit logical OR of immediate data. #xxxx,X:(R2+xx) All registers in DDDDD are permitted except HWS. #xxxx,X:(SP-xx) X:aa represents a 6-bit absolute address. Refer to Absolute Short Address (Direct Addressing): #xxxx,X:aa <aa>...

  • Page 376

    The condition codes are not affected by this instruction. Instruction Fields: Operation Operands Comments Any register Pop a single stack location (No register Simply decrements the SP specified) Timing: 2 oscillator clock cycles Memory: 1 program word A-146 DSP56800 Family Manual...

  • Page 377

    Repeat Next Instruction Operation: Assembler Syntax: LC → TEMP; #xx → LC Repeat next instruction until LC = 1 TEMP → LC LC → TEMP; S → LC Repeat next instruction until LC = 1 TEMP → LC Description: Repeat the single word instruction immediately following the REP instruction the specified number of times.

  • Page 378

    13-bit LC register. Since the loop count is zero, the single word INCW in- struction immediately following the REP instruction is skipped and execution continues with the ASL instruction. The contents of the LC register before the REP loop are restored upon exiting the REP loop. A-148 DSP56800 Family Manual...

  • Page 379

    Repeat Next Instruction Condition Codes Affected: I0 SZ — Set if data limiting occurred using A or B as source operands Instruction Fields: Operation Operands Comments Hardware repeat of a one-word instruction with immediate loop count DDDDD Hardware repeat of a one-word instruction with loop count specified in register Any register allowed except: SP, M01, SR, OMR, and HWS...

  • Page 380

    A accumulator (A0). The example is given assuming that the convergent rounding is selected. Case II is the special case that distinguishes convergent rounding from the two’s-complement round- ing, since it clears the LSB of the MSP after the rounding operation is performed. A-150 DSP56800 Family Manual...

  • Page 381

    Round Accumulator Condition Codes Affected: I0 SZ SZ — Set according to the standard definition of the SZ bit (parallel move) — Set if limiting (parallel move) or overflow has occurred in result — Set if the signed integer portion of A or B result is in use —...

  • Page 382

    ROL A instruction shifts the 16-bit value in the A1 register 1 bit to the left, shifting bit 31 into C, ro- tating C into bit 16, and storing the result back in the A1 register. A-152 DSP56800 Family Manual...

  • Page 383

    Rotate Left Condition Codes Affected: I0 SZ — Set if bit 31 of A or B result is set — Set if bits 31–16 of A or B result are zero — Always cleared — Set if bit 31 of A or B was set prior to the execution of the instruction Instruction Fields: Operation Operands...

  • Page 384

    Prior to execution, the 36-bit B accumulator contains the value $F:0001:00AA. Execution of the ROR B instruction shifts the 16-bit value in the B1 register 1 bit to the right, shifting bit 16 into C, rotating C into bit 31, and storing the result back in the B1 register. A-154 DSP56800 Family Manual...

  • Page 385

    Rotate Right Condition Codes Affected: I0 SZ — Set if bit 31 of A or B result is set — Set if bits 31–16 of A or B result are zero — Always cleared — Set if bit 16 of A or B was set prior to the execution of the instruction Instruction Fields: Operation Operands...

  • Page 386

    MOVE(C) to the SP Any bit-field instruction performed on the SR An RTI instruction cannot be the last instruction in a DO loop (at the LA). An RTI instruction cannot be repeated using the REP instruction. A-156 DSP56800 Family Manual...

  • Page 387

    Return from Interrupt Condition Codes Affected: I0 SZ LF — Set according to the value pulled from the stack I1 — Set according to the value pulled from the stack I0 — Set according to the value pulled from the stack SZ —...

  • Page 388

    Condition Codes Affected: The condition codes are not affected by this instruction. Instruction Fields: Operation Operands Comments Return from subroutine, restoring 16-bit PC from the stack Timing: 10 + rx oscillator clock cycles Memory: 1 program word A-158 DSP56800 Family Manual...

  • Page 389

    Subtract Long with Carry Operation: Assembler Syntax: D - S - C → D (no parallel move) (no parallel move) Description: Subtract the source operand (S) and C of the CCR from the destination operand (D) and store the result in the destination accumulator.

  • Page 390

    — Set if a carry (or borrow) occurs from bit 35 of A or B result Instruction Fields: Operation Operands Comments Subtract with carry (set C bit also) Timing: 2 oscillator clock cycles Memory: 1 program word A-160 DSP56800 Family Manual...

  • Page 391

    STOP STOP Stop Instruction Processing Operation: Assembler Syntax: Enter the stop processing state STOP Description: Enter the stop processing state. All activity in the processor is suspended until the RESET pin is as- serted, the IRQA pin is asserted, or an on-chip peripheral asserts a signal to exit the stop processing state.

  • Page 392

    Bit C is set correctly using word or long word source operands if the extension register of the destina- tion accumulator (A2 or B2) contains sign extension from bit 31 of the destination accumulator (A or B). C is always set correctly using accumulator source operands. A-162 DSP56800 Family Manual...

  • Page 393

    Subtract Condition Codes Affected: I0 SZ SZ — Set according to the standard definition of the SZ bit (parallel move) — Set if limiting (parallel move) or overflow has occurred in result — Set if the signed integer portion of A or B result is in use —...

  • Page 394

    2 + mv oscillator clock cycles for SUB instructions with a parallel move Refer to previous tables for SUB instructions without a parallel move Memory: 1 program word for SUB instructions with a parallel move Refer to previous tables for SUB instructions without a parallel move A-164 DSP56800 Family Manual...

  • Page 395

    Software Interrupt Operation: Assembler Syntax: Begin SWI exception processing Description: Suspend normal instruction execution and begin SWI exception processing. The interrupt priority lev- el, specified by the I1 and I0 bits in the SR, is set to the highest interrupt priority level upon entering the interrupt service routine.

  • Page 396

    (R0 or R1 for the Tcc instruction) is changed using a move-type instruction, the new contents of the destination address register will not be available for use during the following instruction (that is, there is a single-instruction-cycle pipeline delay). A-166 DSP56800 Family Manual...

  • Page 397

    Transfer Conditionally Example: X0,A ; compare X0 and A (sort for minimum) R0,R1; transfer X0 → A and R0 → R1 if X0 < A X0,A Explanation of Example: In this example, the contents of the 16-bit X0 register are transferred to the 36-bit A accumulator, and the contents of the 16-bit R0 address register are transferred to the 16-bit R1 address register if the specified condition is true.

  • Page 398

    B into the 36-bit A accumulator. Condition Codes Affected: I0 SZ SZ — Set according to the standard definition of the SZ bit (parallel move) — Set if data limiting has occurred during parallel move A-168 DSP56800 Family Manual...

  • Page 399

    Transfer Data ALU Register Instruction Fields: Operation Operands Comments DD,F Transfer register to register Transfer one accumulator to another (36-bits) Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination X0,F X:(Rn)+ Y1,F X:(Rn)+N Y0,F F = A,B Timing: 2 + mv oscillator clock cycles...

  • Page 400

    — Always cleared — Always cleared See Section 3.6.2, “36-Bit Destinations—CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Desti- nations—CC Bit Set,” on page 3-34 for the case when the CC bit is set. A-170 DSP56800 Family Manual...

  • Page 401

    Test Accumulator Instruction Fields: Operation Operands Comments Test 36-bit accumulator Data ALU Operation Parallel Memory Read or Write Operation Registers Memory Access Source or Destination X:(Rn)+ X:(Rn)+N Timing: 2 + mv oscillator clock cycles Memory: 1 program word Instruction Set Details A-171...

  • Page 402

    Condition Codes Affected: I0 SZ — Set if bit 15 (bit 31 of A or B) of result is set — Set if result equals zero — Always cleared — Always cleared A-172 DSP56800 Family Manual...

  • Page 403

    TSTW TSTW Test Register or Memory Instruction Fields: Operation Operands Comments TSTW DDDDD Test 16-bit word in register. All registers allowed (except HWS) except HWS. Limiting is not performed if an accu- mulator is specified. X:(Rn) Test a word in memory using appropriate address- ing mode.

  • Page 404

    DSP to exit the wait state and a minimum of 28T cycles to a maximum of 31T cycles (see the appropriate data sheet). Memory: 1 program word A-174 DSP56800 Family Manual...

  • Page 405: Table B-1 Benchmark Summary

    Appendix B DSP Benchmarks The following benchmarks illustrate source code syntax and programming techniques for the DSP56800. The assembly language source is organized into five columns, as shown in Example B-1. Example B-1. Source Code Layout Label Opcode Operands Data bus...

  • Page 406: B.1 Benchmark Code

    (N - p / 2) Benchmark Code The following source code lists all the “defines” for the benchmarks. page 132 ; define section $100 $100 $200 $200 $300 $300 $400 OUTPUT $500 output $FFF1 INPUT $501 input $FFF1 DSP56800 Family Manual...

  • Page 407: B.1.1 Real Correlation Or Convolution (fir Filter)

    state ntaps mask image dividend divisor paddr qaddr tablebase equ frame $100 shift ; shift constant table $180 ; base address of a-law table p:$40 B.1.1 Real Correlation or Convolution (FIR Filter) ; c(n) = SUM(I=0,...,N-1) { a(I) * b(n-I) } MOVE #AD,R0 MOVE #BD,R3 X:(R0)+,Y0...

  • Page 408: B.1.2 N Complex Multiplies, B.1.3 Complex Correlation Or Convolution (complex Fir)

    ; ci(n) = SUM(I=0,...,N-1) Y0=ai X0=bi ; { ar(I) * bi(n-I) + ai(I) * br(n-I) } MOVE #AD,R0 MOVE #BD,R3 X:(R0)+,Y0 X:(R3)+,Y1 #N,END_DOB Y0,Y1,A X:(R3)+,X0 ar*br ,ai,bi Y0,X0,B X:(R0)+,Y0 ar*bi Y0,Y1,B X:(R3)+,Y1 ar*bi+ai*br,ar -Y0,X0,A ar*br-ai*bi MOVE X:(R0)+,Y0 DSP56800 Family Manual...

  • Page 409: B.1.4 Nth Order Power Series (real, Fractional Data)

    END_DOB _______ Total: 5N+11 B.1.4 Nth Order Power Series (Real, Fractional Data) ; c = SUM(I=0,...,N) { a(I) * b**I } ; = [[[a(n) *b+a(n-1)] *b+a(n-2)]*b+a(n-3)]..MOVE #BD,R1 MOVE #AD,R0 MOVE X:(R1),Y0 MOVE Y0,Y1 MOVE X:(R0)+,A get a(n) MOVE X:(R0)+,B get a(n-1) #NUM/2,END_DOC A1,Y0,B...

  • Page 410: B.1.6 N Radix 2 Fft Butterflies

    ; xi = ai + wi * br + wr * bi ; yr = ar - wr * br + wi * bi = 2 * ar - xr ; yi = ai - wi * br - wr * bi = 2 * ai - xi DSP56800 Family Manual...

  • Page 411: B.1.7 Lms Adaptive Filter

    move x:(r1)+,y0 x:(r3)+,x0 ; y0=wr ; x0=br move x:(r0),b ;b=ar move x:(r1)+n,y1 ; y1=wi ; save r1, update r1 to point last bi/yi move #0,n ; emulate X:(Rn) adr mode #n,end_bfly push push br y0,x0,b x:(r3)+,x0 b=ar+wrbr macr -y1,x0,b b=xr move a,x:(r1)+ move...

  • Page 412

    Only the instructions relating to the filtering and coefficient update are shown as part of the benchmark. Instructions executed only once (for initialization) or instructions that may be user application dependent are not included in the benchmark. DSP56800 Family Manual...

  • Page 413: B.1.7.1 Single Precision

    B.1.7.1 Single Precision Figure B-3 shows a memory map for this implementation of the single-precision LMS adaptive filter. X memory x(n) x(n-1) x(n-N+1) r3,r1 c(N-1) AA0081 Figure B-3. LMS Adaptive Filter—Single Precision Memory Map move #XM,r0 ; start of X move #N-1,m0 ;...

  • Page 414: B.1.7.2 Double Precision

    ; a1=c0h move x:(r3)+,a0 ; a0=col #ntaps,_coefupdate ; update coef. x0,y0,a x:(r0)+,y0 u e(n) x(n)+c; fetch x(n) move a,x:(r1)+ save updated c()h move a0,x:(r1)+ ; save updated c()l move x:(r3)+,a ; fetch next c()h B-10 DSP56800 Family Manual...

  • Page 415: B.1.7.3 Double Precision Delayed

    move x:(r3)+,a0 ; fetch next c()l _coefupdate move #-2,n ; adjustment for ; filtering move x:(r0)+n,y0 ; update r0 _______ Total: 6N+18 B.1.7.3 Double Precision Delayed Figure B-5 shows a memory map for this implementation of the double-precision delayed LMS adaptive filter.

  • Page 416: B.1.8 Vector Multiply-accumulate

    Figure B-6 gives a graphical overview and memory map for the vector multiply-accumulate code. X memory AA0084 Figure B-6. Vector Multiply-Accumulate move #ad,r0 point to vec a move #bd,r3 point to vec b move #cd,r1 point to vec c B-12 DSP56800 Family Manual...

  • Page 417: B.1.9 Energy In A Signal

    x:(r3)+,x0 move x:(r0)+,a #NUM,_vmac y0,x0,a x:(r0)+,y1 x:(r3)+,x0 y1,a a,x:(r1)+ _vmac _______ Total: 2N+11 B.1.9 Energy in a Signal This code calculates the energy in a signal by summing together the square of each sample. move #ad,r0 point to signal a x:(r0)+,a #NUM,_energy y0,y0,a...

  • Page 418: B.1.10 [3x3][1x3] Matrix Multiply

    +a22*b2 macr y0,x0,a x:(r0)+,y0 x:(r3)+,x0 +a23*b3 move a,x:(r2)+ store c2 y0,x0,a x:(r0)+,y0 x:(r3)+,x0 a31*b1 y0,x0,a x:(r0)+,y0 x:(r3)+,x0 +a32*b2 macr y0,x0,a +a33*b3->c3 move a,x:(r2)+ store c3 _______ Total: B-14 DSP56800 Family Manual...

  • Page 419: B.1.11 [nxn][nxn] Matrix Multiply

    B.1.11 [NxN][NxN] Matrix Multiply The matrix multiplications are for square NxN matrices (all elements are in row-major format). Figure B-8 gives a graphical overview and memory map of an [NxN][NxN] matrix multiply. X memory a11 .. a1k .. a1N b11 .. b1k .. b1N ak1 ..

  • Page 420

    A move b,y1 move #bd,r1 first element B erows _______ Words: Cycles: Total: ((9+(N-1))N+10)N+12)= N +10N+17 B-16 DSP56800 Family Manual...

  • Page 421: B.1.12 N Point 3x3 2-d Fir Convolution, Table B-2 Variable Descriptions

    B.1.12 N Point 3x3 2-D FIR Convolution The two-dimensional FIR uses a 3x3 coefficient mask as shown in Figure B-9. AA0087 Figure B-9. 3x3 Coefficient Mask The image is an array of 512 pixels x 512 pixels. To provide boundary conditions for the FIR filtering, the image is surrounded by a set of zeros such that the image is actually stored as a 514x514 array (see Figure B-10).

  • Page 422

    +im(3,2)*c32 move #0,r3 back to first coeff move y1,n row i to i+1 adjust macr y0,x0,a x:(r0)+,y0 x:(r3)+,x0 +im(3,3)*c33 move a,x:(r2)+ cols adjust pointers for frame boundary (r0)+ adjust r0 (r0)+ (r2)+ adjust r2 (r2)+ rows B-18 DSP56800 Family Manual...

  • Page 423

    ; _______ Total: +11N+16 Kernel: 13 DSP Benchmarks B-19...

  • Page 424: B.1.13 Sine-wave Generation, B.1.13.1 Double Integration Technique

    F0 = Oscillation Frequency Fs = Sampling Frequency AA0089 Figure B-11. Sine Wave Generator—Double Integration Technique move #$4000,a move #0,n move #$4532,y1 move #$1,r1 move y1,y0 x0,loop1 y1,b1,a b,x:(r1)+n -y0,a1,b loop1 move b,x:(r1) _______ Total: 2N+12 B-20 DSP56800 Family Manual...

  • Page 425: B.1.13.2 Second Order Oscillator

    B.1.13.2 Second Order Oscillator Figure B-12 gives a graphical overview of a second order oscillator. a = Stored initial value which is the desired tone amplitude sin(w – x0 = 2*cos( 2π Fs/F0) F0 = Oscillation Frequency Fs = Sampling Frequency AA0090 Figure B-12.

  • Page 426: B.1.14 Array Search, B.1.14.1 Index Of The Highest Signed Value

    (r1)- (r1)- _______ Total: 10 4N+8 (worst case) B.1.14.2 Index of the Highest Positive Value move #AD,r0 x:(r0)+,x0 #N/2,end_lp3 x0,a x:(r0)+,y0 x0,a r0,r1 y0,a x:(r0)+,x0 y0,a r0,r1 end_lp3 (r1)- (r1)- _______ Total: 10 2N+8 (worst case) B-22 DSP56800 Family Manual...

  • Page 427: B.1.15 Proportional Integrator Differentiator (pid) Algorithm

    B.1.15 Proportional Integrator Differentiator (PID) Algorithm The proportional integrator differentiator (PID) algorithm is the most commonly used algorithm in control applications. Figure B-13 gives a graphical overview and memory map of this implementation of a proportional integrator differentiator. X memory y(n) x(n) x(n-1)

  • Page 428: B.1.16 Autocorrelation Algorithm

    1 y(n) in b _________ B.1.16 Autocorrelation Algorithm move #cor,r1 move #frame,r2 #lpc+1,_loop1 move r2,r3 move #frame,r0 (r2)+ move lc,y1 move #>N-(p+1),a y1,a x:(r0)+,y0 x:(r3)+,x0 y0,x0,b x:(r0)+,y0 x:(r3)+,x0 move b0,x:(r1)+ move b1,x:(r1)+ _loop1 ; ______ (p+1) (N-p/2)+15(p+1) +6 B-24 DSP56800 Family Manual...

  • Page 429

    Glossary See Section A.1, “Notation,” on page A-1 for notations and symbols not listed here. analog-to-digital application development module application development system address generation unit arithmetic logic unit accumulator shifter bus control register BE1–BE0 breakpoint enable bits BK4–BK0 breakpoint configuration bits BS1–BS0 breakpoint selection bits Glossary...

  • Page 430

    CGDB core global data bus CMOS complementary metal oxide semiconductor COFF common object file format computer operating properly COPDIS COP timer disable central processing unit carry bit set digital-to-analog digital-to-analog converter debug request mask bit DSP56800 Family Manual...

  • Page 431

    digital signal processor extension bit EM1–EM0 event modifier bits external X memory bit extension register FIFO halt bit FIFO first-in-last-out greater than or equal to GPIO general-purpose input/output greater than graphical user interface hardware breakpoint occurrence high high or same Glossary...

  • Page 432

    JTAG Joint Test Access Group input/output interrupt priority level interrupt priority register K&R Kernighan and Ritchie limit bit loop address register loop counter register less than or equal to loop flag bit LIFO last-in-first-out DSP56800 Family Manual...

  • Page 433

    least significant; low or same least significant bit least significant portion less than MA, MB operating modes multiply-accumulate microcontroller unit MIPS million instructions per second modifier register mode register most significant most significant bit most significant portion Glossary...

  • Page 434

    OnCE breakpoint counter ODEC OnCE decoder OISR OnCE input shift register OMAC OnCE memory address comparator OMAL OnCE breakpoint address latch operating mode register OPABDR OnCE PAB decode register OPABER OnCE PAB execute register OPABFR OnCE PAB fetch register DSP56800 Family Manual...

  • Page 435

    OPDBR OnCE PDB register OPGDBR Once PGDB register OS1, OS0 OnCE status bits OnCE status register OnCE™ On-Chip Emulation (unit) P2–P0 program counter extension program address bus program counter PGDB peripheral global data bus power-down mode bit phase-locked loop rounding bit address registers (R0–R3) saturation bit Glossary...

  • Page 436

    World Wide Web external XAB1 X memory address bus one DSP56800 Family Manual...

  • Page 437

    XAB2 X memory address bus two XDB2 X memory data bus two X/P memory bit zero bit Glossary...

  • Page 438

    G-10 DSP56800 Family Manual...

  • Page 439

    Index ASR A-42 ASRAC A-44 A accumulator 3-2 ASRR A-46 A0, see A accumulator A1, see A accumulator A2 accumulator extension register 3-2 B accumulator 3-2 ABS A-28 B0, see B accumulator Absolute Value ABS A-28 B1, see B accumulator accumulator extension register (A2 or B2) 3-4 B2 accumulator extension register 3-2 accumulator extension registers 3-2...

  • Page 440

    DO looping 5-15 interrupt latency 7-16 DO loops 8-20 interrupt mask (I1 and I0) 5-8 DSP56800 1-1 interrupt pipeline 7-14 DSP56800 core 1-2 interrupt priority level (IPL) 5-3 Interrupt Priority Register (IPR) 7-9 interrupt priority structure 7-8 interrupt sources 7-9 Index-ii...

  • Page 441

    6-7 integer 3-20 logical operations 3-19 multi-precision 3-23 Logical Right Shift with Accumulate LSRAC A-99 unsigned 3-22 Logical Shift Left LSL A-93 Multiply Accumulate and Round MACR A-105 Logical Shift Right LSR A-97 Multiply-Accumulate MAC A-103 DSP56800 Family Manual Index-iii...

  • Page 442

    Rounding bit (R) 5-12 Parallel Move—Dual Parallel Reads A-114 RTI A-156 parallel moves 6-1 RTS A-158 Parallel Move—Single Parallel Move A-112 parameters, passing subroutine 8-28 PC, see Program Counter (PC) saturation 3-26 PDB, see program data bus (PDB) Index-iv DSP56800 Family Manual...

  • Page 443

    Test Bitfield and Change BFCHG A-50 Test Bitfield and Clear BFCLR A-52 Test Bitfield and Set BFSET A-54 Test Bitfield High BFTSTH A-56 Test Bitfield Low BFTSTL A-58 Test Register or Memory TSTW A-172 TFR A-168 DSP56800 Family Manual Index-v...

  • Page 444

    Index-vi DSP56800 Family Manual...

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