Figure 2-1 Dsp56800 Core Block Diagram - Motorola DSP56800 Manual

Core Architecture Overview
Program
Controller
SR OMR
LA LC
PC HWS
Bus and Bit
Manipulation
Unit
OnCE
Note that Figure 2-1 illustrates two methods for connecting peripherals to the DSP56800 core: using the
Motorola-standard IP-BUS interface or via a dedicated peripheral global data bus (PGDB). When the
IP-BUS interface is used, peripheral registers may be memory mapped into any data (X) memory address
range and are accessed with standard X-memory reads and writes. When the PGDB interface is used,
peripheral registers are mapped to the last 64 locations in X memory and are accessed with a special
memory addressing mode (see Section 4.2.4.3, "I/O Short Address (Direct Addressing): <pp>," on
page 4-23).
The interface method used to connect to peripherals is dependent on the specific DSP56800-based device
being used. Consult your device user's manual for more information on peripheral interfacing.
2-2
AGU
M01 N
Instr. Decoder
and
Interrupt Unit
Data
Limiter
ALU
Y1 Y0 X0 A2 A1 A0
Figure 2-1. DSP56800 Core Block Diagram
DSP56800 Family Manual
SP
R0
MOD.
+/-
ALU
R1
R2
R3
XAB1
XAB2
PAB
PDB
CGDB
XDB2
PGDB
B2 B1 B0
MAC
and
ALU
Program
Memory
Data
Memory
External
Bus
Interface
IP-BUS
Interface