Integer Multiplication; Figure 3-11 Mpy Operation-Fractional Arithmetic - Motorola DSP56800 Manual

Data Arithmetic Logic Unit
Signed Fractional
Input Operands
Signed
Intermediary
Multiplier Result
Signed Fractional
MPY Result
3.3.5.2

Integer Multiplication

Two techniques for performing integer multiplication on the DSP core are as follows:
• Using the IMPY(16) instruction to generate a 16-bit result in the MSP of an accumulator
• Using the MPY and MAC instructions to generate a 36-bit full precision result
Each technique has its advantages for different types of computations.
An examination of the instruction set shows that for execution of single precision operations, most often
the instructions operate on the MSP (bits 31–16) of the accumulator instead of the LSP (bits 15–0). This is
true for the LSL, LSR, ROL, ROR, NOT, INCW, and DECW instructions and others. Likewise, for the
parallel MOVE instructions, it is possible to move data to and from the MSP of an accumulator, but this is
not true for the LSP. Thus, an integer multiplication instruction that places its result in the MSP of an
accumulator allows for more efficient computing. This is the reason why the IMPY(16) instruction places
its results in bits 31–16 of an accumulator. The limitation with the IMPY(16) instruction is that the result
must fit within 16 bits or there is an overflow.
Figure 3-12 on page 3-21 shows the multiply operation for integer arithmetic. The multiplication of two
16-bit signed integer operands using the IMPY(16) instruction gives a 16-bit signed integer result that is
placed in the MSP (A1 or B1) of the accumulator. The corresponding extension register (A2 or B2) is filled
with sign extension and the LSP (A0 or B0) remains unchanged.
3-20
Input Operand 1
s
s s
EXP
Figure 3-11. MPY Operation—Fractional Arithmetic
DSP56800 Family Manual
s
16 Bits
16
32 Bits
MSP
36 Bits
Input Operand 2
16 Bits
16
LSP
AA0043
0
0