Bfchg - T - Motorola DSP56800 Manual

16-bit digital signal processor
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BFCHG
Operation:
(<bit field> of destination) → (<bit field> of destination)BFCHG
(<bit field> of destination) → (<bit field> of destination)BFCHG
Description: Test all selected bits of the destination operand. If all selected bits are set, C is set; otherwise, C is
cleared. Then complement the selected bits and store the result in the destination memory location. The
bits to be tested are selected by a 16-bit immediate value in which every bit set is to be tested and
changed. This instruction performs a read-modify-write operation on the destination memory location
or register and requires two destination accesses.
Usage:
This instruction is very useful in performing I/O and flag bit manipulation.
Example:
BFCHG
Before Execution
X:$FFE2
SR
Explanation of Example:
Prior to execution, the 16-bit X memory location X:$FFE2 contains the value $0010. Execution of the
instruction tests the state of the bits 4, 8, and 9 in X:$FFE2; does not set C (because all of the CCR bits
were not set); and then complements the bits.
Condition Codes Affected:
15
14
LF
*
For destination operand SR:
For other destination operands:
Note:
If all bits in the mask are set to zero, the destination is unchanged, and the C bit is set.
A-50
Test Bit Field and Change
#$0310,X:<<$FFE2
0010
0001
MR
13
12
11
10
9
*
*
*
*
I1
?
— Changed if specified in the field
L
— Set if data limiting occurred during 36-bit source move
C
— Set if all bits specified by the mask are set
Clear if not all bits specified by the mask are set
DSP56800 Family Manual
Assembler Syntax:
#iiii,X:<ea>
#iiii,D
;test and change bits 4, 8, and 9
;in a peripheral register
After Execution
X:$FFE2
SR
CCR
8
7
6
5
4
L
I0
SZ
E
U
BFCHG
0300
0000
3
2
1
0
C
N
Z
V

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