Motorola DSP56800 Manual page 393

SUB
Condition Codes Affected:
15 14
LF *
See Section 3.6.5, "16-Bit Destinations," on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, "36-Bit Destinations—CC Bit Set," on page 3-34 and Section 3.6.4, "20-Bit Desti-
nations—CC Bit Set," on page 3-34 for the case when the CC bit is set.
Instruction Fields:
Operation
SUB
Data ALU Operation
Operation
SUB
Subtract
MR
13 12 11 10 9
* * * * I1
SZ — Set according to the standard definition of the SZ bit (parallel move)
L — Set if limiting (parallel move) or overflow has occurred in result
E — Set if the signed integer portion of A or B result is in use
U — Set according to the standard definition of the U bit
N — Set if bit 35 of A or B result is set except during saturation
Z — Set if A or B result equals zero
V — Set if overflow has occurred in A or B result
C — Set if a carry (or borrow) occurs from bit 35 of A or B result
Operands C
DD,FDD 2
F1,DD
~F,F
Y,F
X:(SP-xx),FDD 6
X:aa,FDD 4
X:xxxx,FDD 6
#xx,FDD 4
#xxxx,FDD 6
Registers
X0,F
Y1,F
Y0,F
A,B
B,A
(F = A or B)
Instruction Set Details
CCR
8 7 6 5 4
I0 SZ L E U N
W
1 36-bit subtract of two registers. 16-bit source regis-
ters are first sign extended internally and concate-
nated with 16 zero bits to form a 36-bit operand.
1 Subtract memory word from register.
1
X:aa represents a 6-bit absolute address. Refer to
Absolute Short Address (Direct Addressing):
2
<aa> on page 4-22.
1 Subtract an immediate value 0–31
2 Subtract a signed 16-bit immediate
Parallel Memory Read or Write
Memory Access Source or Destination
X:(Rn)+
X:(Rn)+N
SUB
3 2 1 0
Z V C
Comments
X0
Y1
Y0
A
B
A1
B1
A-163