Motorola DSP56800 Manual page 403

TSTW
Instruction Fields:
Operation
TSTW
Timing: Refer to the preceding Instruction Fields table
Memory: Refer to the preceding Instruction Fields table
Test Register or Memory
Operands C
DDDDD 2
(except HWS)
X:(Rn) 2
X:(Rn)+ 2
X:(Rn)- 2
X:(Rn+N) 4
X:(Rn)+N 2
X:(Rn+xxxx) 6
X:(R2+xx) 4
X:(SP-xx) 4
X:aa 2
X:pp 2
X:xxxx 4
(Rn)- 2
Instruction Set Details
W
1 Test 16-bit word in register. All registers allowed
except HWS. Limiting is not performed if an accu-
mulator is specified.
1 Test a word in memory using appropriate address-
ing mode.
1
1
1
1
2
1
1
X:aa represents a 6-bit absolute address. Refer to
Absolute Short Address (Direct Addressing):
1
<aa> on page 4-22.
1
X:pp represents a 6-bit absolute I/O address. Refer
to I/O Short Address (Direct Addressing): <pp>
2
on page 4-23.
1
Test and decrement AGU register
TSTW
Comments
A-173