Figure 7-1 Interrupt Processing - Motorola DSP56800 Manual

Interrupts and the Processing States
2. The request for an interrupt by a particular source is latched in an interrupt-pending flag if
it is an edge or non-maskable interrupt (all other interrupts are not latched and must remain
asserted in order to be serviced). For peripherals that can generate more than one interrupt
request and have more than one interrupt vector, the interrupt arbiter only sees one request
from the peripheral active at a time.
3. All pending interrupt requests are arbitrated to select which interrupt will be processed. The
arbiter automatically ignores any interrupts with an interrupt priority level (IPL) lower than
the interrupt mask level specified in the SR. If there are any remaining requests, the arbiter
selects the remaining interrupt with the highest IPL, and the chip enters the exception
processing state (see Figure 7-1).
4. The interrupt controller then freezes the program counter (PC) and fetches the JSR
instruction located at the two interrupt vector addresses associated with the selected
interrupt. It is required that the instruction located at the interrupt vector address must be a
two-word JSR instruction. Note that only the second word of the JSR instruction is fetched;
the first word of the JSR is provided by the interrupt controller.
5. The interrupt controller places this JSR instruction into the instruction stream and then
releases the PC, which is used for the next instruction fetch. Arbitration among the
remaining interrupt requests is allowed to resume. The next interrupt arbitration then
begins.
6. The execution of the JSR instruction stacks the PC and the SR as it transfers control to the
first instruction in the interrupt service routine. These two stacked registers contain the
16-bit return address that will later be used to return to the interrupted code, as well as the
condition code state. In addition, the IPL is raised to level 1 to disallow any level 0
interrupts. Note that the OnCE trap, stack error, illegal instruction, and SWI can still
generate interrupts because these are level 1 interrupts and are non-maskable.
The exception processing state is completed when the processor executes the JSR instruction located in the
interrupt vector table and the chip enters the normal processing state. As it enters the normal processing
state, it begins executing the first instruction in the interrupt service routine. Each interrupt service routine
should return to the main program by executing an RTI instruction.
Interrupt routines for level 0 interrupts are interruptible by higher priority interrupts. Figure 7-1 shows an
example of processing an interrupt.
Main
Program
—
$0100
$0101 MACR
MOVE
$0102
MAC
$0103
$0104 REP
$0105 MAC
$0106 —
7-6
Interrupt Service Routine
Interrupt
Recognized
Explicit Return
from Interrupt
Recognized
Figure 7-1. Interrupt Processing
DSP56800 Family Manual
SSI Receive Data
with Exception Status
JSR
$000E
$000F $0300
$0300
ADD
$0301
ASL
$0302
MOVE
$0303 RTI
JSR Instruction
in Vector Table to
Interrupt Service
Routine
AA0056