Lsrr - Motorola DSP56800 Manual

LSRR

Operation:
S1 >> S2 → D
(no parallel move)
Description: Logically shift the first 16-bit source operand (S1) to the right by the value contained in the lowest 4
bits of the second source operand (S2), and store the result in the destination register (D). If the desti-
nation is a 36-bit accumulator, correctly zero extend into the extension register (A2 or B2) and place
zero in the LSP (A0 or B0).
Example:
LSRR
Before Execution
0 3456
A2 A1
Explanation of Example:
Prior to execution, the Y1 register contains the value to be shifted ($AAAA), and the X0 register con-
tains the amount by which to shift ($0004). The contents of the destination register are not important
prior to execution because they have no effect on the calculated value. The LSRR instruction logically
shifts the value $AAAA four bits to the right and places the result in the destination register (A). Since
the destination is an accumulator, the extension word (A2) is filled with sign extension, and the LSP
(A0) is set to zero.
Condition Codes Affected:
15 14
LF *
Multi-Bit Logical Right Shift
Y1,X0,A
3456
A0
Y1
AAAA
X0
0004
MR
13 12 11 10 9
* * * * I1
N — Set if bit 35 of A or B result is set except during saturation
Z — Set if A or B result equals zero
Instruction Set Details
Assembler Syntax:
LSRR S1,S2,D
; right shift of 16-bit Y1 by X0
After Execution
0 0AAA
A2 A1
CCR
8 7 6 5 4
I0 SZ L E U
LSRR
(no parallel move)
0000
A0
Y1
AAAA
X0
0004
3 2 1 0
N Z
V C
A-101