Architecture And Programming Model - Motorola DSP56800 Manual

Address Generation Unit
This chapter covers the architecture and programming model of the address generation unit, its addressing
modes, and a discussion of the linear and modulo arithmetic capabilities of this unit. It concludes with a
discussion of pipeline dependencies related to the address generation unit.
4.1

Architecture and Programming Model

The major components of the address generation unit are as follows:
• Four address registers (R0-R3)
• A stack pointer register (SP)
• An offset register (N)
• A modifier register (M01)
• A modulo arithmetic unit
• An incrementer/decrementer unit
The AGU uses integer arithmetic to perform the effective address calculations necessary to address data
operands in memory. The AGU also contains the registers used to generate the addresses. It implements
linear and modulo arithmetic and operates in parallel with other chip resources to minimize
address-generation overhead.
Two ALUs are present within the AGU: the modulo arithmetic unit and the incrementer/decrementer unit.
The two arithmetic units can generate up to two 16-bit addresses and two address updates every instruction
cycle: one for XAB1 and one for XAB2 for instructions performing two parallel memory reads. The AGU
can directly address 65,536 locations on XAB1 and 65,536 locations on the PAB. The AGU can directly
address up to 65,536 locations on XAB2, but can only generate addresses to on-chip memory. The two
ALUs work with the data memory to access up to two locations and provide two operands to the data ALU
in a single cycle. The primary operand is addressed with the XAB1, and the second operand is addressed
with the XAB2. The data memory, in turn, places its data on the core global data bus (CGDB) and the
second external data bus (XDB2), respectively (see Figure 4-1 on page 4-3). See Section 6.1, "Introduction
to Moves and Parallel Moves," on page 6-1 for more discussion on parallel memory moves.
4-2 DSP56800 Family Manual