Figure 3-16 Two's-Complement Rounding - Motorola DSP56800 Manual

Data Arithmetic Logic Unit
Case I
: A0 < 0.5 ($8000), then round down
Before Rounding
A2 A1
XXXX XX...XX0100
36 31
Case II
: A0 >= 0.5 ($8000), then round up
Before Rounding
A2 A1
XXXX XX...XX0100
36 31
*A0 is always clear; performed during RND, MPYR, MACR
Once the rounding bit has been programmed in the OMR register, there is a delay of one instruction cycle
before the new rounding mode becomes active.
3-32
A0
011XXX...XX
15 0
A0
1110XX...XX
15 0
Figure 3-16. Two's-Complement Rounding
DSP56800 Family Manual
After Rounding
A2 A1
XXXX XX...XX0100
36 31
After Rounding
A2 A1
XXXX XX...XX0101
36 31
A0*
0000...0000
15 0
A0*
0000...0000
15 0
AA0050