Motorola DSP56800 Manual page 332

LSRR
Instruction Fields:
Operation
LSRR
Timing: 2 oscillator clock cycles
Memory:
1 program word
A-102
Multi-Bit Logical Right Shift
Operands C
Y1,X0,FDD 2
Y0,X0,FDD
Y1,Y0,FDD
Y0,Y0,FDD
A1,Y0,FDD
B1,Y1,FDD
DSP56800 Family Manual
W
1 Logical shift right of the first operand by value speci-
fied in four LSBs of the second operand; places
result in FDD (when result is to an accumulator F,
zero extends into F2)
LSRR
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