Figure A-1 Dsp56800 Core Programming Model; A.2 Programming Model - Motorola DSP56800 Manual

A.2 Programming Model
The registers in the DSP56800 core programming model are shown in Figure A-1.
15
15
R0
R1
R2
R3
SP
Pointer
Registers
15
PC
Program
Counter
15
Hardware Stack (HWS)
Data Arithmetic Logic Unit
Data ALU Input Registers
X0 Y
0
Accumulator Registers
35 32 31
A A2 A1
3 0 15
35 32 31
B B2 B1
3 0 15
Address Generation Unit
0 15
Program Controller Unit
0 15
MR
Register (SR)
0 15
Software Stack
(Located in X Memory)
Figure A-1. DSP56800 Core Programming Model
Instruction Set Details
31 16 15
Y1
15 0 15
16 15
A0
0 15
16 15
B0
0 15
0
N
Offset
Register
8 7 0
CCR
Status
0
0
Y0
0
0
0
0
0
15 0
M01
Modifier
Register
15 0
OMR
Operating Mode
Register
15 0
LA
Loop Address
12 0
LC
Loop Counter
AA0007
A-5