Lsl - Motorola DSP56800 Manual

LSL

Operation:
(see following figure)
C Unch.
Description: Logically shift 16 bits of the destination operand (D) 1 bit to the left and store the result in the desti-
nation. If the destination is a 36-bit accumulator, the result is stored in the MSP of the accumulator (A1
or B1), and the remaining portions of the accumulator (A2, B2, A0, B0) are not modified. The MSB
of the destination (bit 31 if the destination is a 36-bit accumulator) prior to the execution of the instruc-
tion is shifted into C, and zero is shifted into the LSB of D1 (bit 16 if the destination is a 36-bit accu-
mulator).
Example:
LSL
Before Execution
6 8000
B2 B1
SR
0300
Explanation of Example:
Prior to execution, the 36-bit B accumulator contains the value $6:8000:00AA. Execution of the
LSL B instruction shifts the 16-bit value in the B1 register 1 bit to the left and stores the result back
in the B1 register. C is set by the operation because bit 31 of A1 was set prior to the execution of the
instruction. The Z bit of CCR (bit 2) is also set because the result in A1 is zero.
Logical Shift Left
Unchanged
D2 D1
B
00AA
B0
Instruction Set Details
Assembler Syntax:
LSL
0
D0
; multiply B1 by 2
After Execution
6 0000
B2 B1
SR
0305
LSL
D
(no parallel move)
00AA
B0
A-93