Program Controller And Hardware Looping Unit - Motorola DSP56800 Manual

Core Architecture Overview
The address registers are 16-bit registers that may contain an address or data. Each address register can
provide an address for the XAB1 and PAB address buses. For instructions that read two values from X data
memory, R3 provides an address for the XAB2, and R0 or R1 provides an address for the XAB1. The
modifier and offset registers are 16-bit registers that control updating of the address registers. The offset
register can also be used to store 16-bit data. AGU registers may be read or written by the CGDB as 16-bit
operands. Refer to Chapter 4, "Address Generation Unit," for a detailed description of the AGU.
2.1.3

Program Controller and Hardware Looping Unit

The program controller performs the following:
• Instruction prefetch
• Instruction decoding
• Hardware loop control
• Interrupt (exception) processing
Instruction execution is carried out in other core units such as the data ALU, AGU, or bit-manipulation
unit. The program controller consists of the following:
• A program counter unit
• Instruction latch and decoder
• Hardware looping control logic
• Interrupt control logic
• Status and control registers
Located within the program controller are the following:
• Four user-accessible registers:
— Loop address register (LA)
— Loop count register (LC)
— Status register (SR)
— Operating mode register (OMR)
• A program counter (PC)
• A hardware stack (HWS)
In addition to the tasks listed above, the program controller also controls the memory map and operating
mode. The operating mode and memory map are programmable via the OMR, and are established after
reset by external interface pins.
The HWS is a separate internal last-in-first-out (LIFO) buffer of two 16-bit words that stores the address of
the first instruction in a hardware DO loop. When a new hardware loop is begun by executing the DO
instruction, the address of the first instruction in the loop is stored (pushed) on the "top" location of the
HWS, and the LF bit in the SR is set. The previous value of the loop flag (LF) bit is copied to the OMR's
NL bit. When an ENDDO instruction is encountered or a hardware loop terminates naturally, the 16-bit
address in the "top" location of the HWS is discarded, and the LF bit is updated with the value in the
OMR's nested looping (NL) bit.
The program controller is described in detail in Chapter 5, "Program Controller." For more details on
program looping, refer to Section 5.3, "Program Looping," on page 5-14 and Section 8.6, "Loops," on
page 8-20. For information on reset and interrupts, refer to Chapter 7, "Interrupts and the Processing
States."
2-4 DSP56800 Family Manual