External Hardware Interrupt Sources - Motorola DSP56800 Manual

Interrupts and the Processing States
When an interrupt request is recognized and accepted by the DSP core, a two-word JSR instruction is
fetched from the interrupt vector table. Because the program flow is directed to a different starting address
within the table for each different interrupt, the interrupt structure can be described as "vectored." A
vectored interrupt structure has low execution overhead. If it is known beforehand that certain interrupts
will not be used or enabled, those locations within the table can instead be used for program or data
storage.
7.3.5.1

External Hardware Interrupt Sources

The external hardware interrupt sources are listed below:
• RESET pin
• IRQA pin—priority level 0
• IRQB pin—priority level 0
An assertion of the RESET is not truly an interrupt, but rather it forces the chip into the reset processing
state. Likewise, for any DSP chip that contains a COP timer, a time-out on this timer can also place the
chip into the reset processing state. The reset processing state is at the highest priority and takes
precedence over any interrupt, including an interrupt in progress.
Assertions on the IRQA and IRQB pins generate IRQA and IRQB interrupts, which are priority level 0
interrupts and are individually maskable. The IRQA and IRQB interrupt pins are internally synchronized
with the processor's internal clock and can be programmed as level-sensitive or edge-sensitive.
Edge-sensitive interrupts are latched as pending when a falling edge is detected on an IRQ pin. The IRQ
pin's interrupt-pending bit remains set until its associated interrupt is recognized and serviced by the DSP
core. Edge-sensitive interrupts are automatically cleared when the interrupt is recognized and serviced by
the DSP core. In an edge-sensitive interrupt the interrupt-pending bit is automatically cleared when the
second vector location is fetched.
Level-sensitive interrupts, on the other hand, are never latched but go directly into the interrupt controller.
A level-sensitive interrupt is examined and processed when the IRQ pin is low and the interrupt arbiter
allows this interrupt to be recognized. Since there is no interrupt-pending bit associated with
level-sensitive interrupts, the interrupt cannot not be cleared automatically when serviced; instead, it must
be explicitly cleared by other means to prevent multiple interrupts.
On all level-sensitive interrupts, the interrupt must be externally released
before interrupts are internally re-enabled. Otherwise, the processor will
be interrupted repeatedly until the release of the level-sensitive interrupt.
When either the IRQA or IRQB pin is disabled in the IPR, any interrupt request on its associated pin is
ignored, regardless of whether the input was defined as level-sensitive or edge-sensitive. If the interrupt
input is defined as edge-sensitive, its interrupt-pending bit will remain in the reset state for as long as the
interrupt pin is disabled. If the interrupt is defined as level-sensitive, its edge-detection latch will stay in the
reset state. If the level-sensitive interrupt is disabled while it is pending, it will be cancelled. However, if
the interrupt has been fetched, it normally will not be cancelled.
The level-sensitive interrupt capability is useful for the case where there is more than one external interrupt
source, yet only one IRQ pin is available. In this case the interrupts are wire ORed onto a single IRQ pin
with a resistor pull-up, and any one of these can assert an interrupt. It is important that the interrupt service
routine poll each device, and, after finding the source of the interrupt, it must clear the conditions causing
the interrupt request.
7-10
NOTE:
DSP56800 Family Manual