Figure 5-4 Status Register Format; Carry (C)—Bit 0; Overflow (V)—Bit 1; Zero (Z)—Bit 2 - Motorola DSP56800 Manual

16-bit digital signal processor
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SR
Status Register
Reset = $0300
Read/Write
LF—Loop Flag
I1,I0—Interrupt Mask
SZ—Size
L—Limit
E—Extension
U—Unnormalized
N—Negative
Z—Zero
V—Overflow
C—Carry
* Indicates reserved bits that are read as zero and should be written with zero for future compatibility
5.1.8.1
Carry (C)—Bit 0
The carry (C) bit (SR bit 0) is set if a carry is generated out of the MSB of the result for an addition. It also
is set if a borrow is generated in a subtraction. If the CC bit in the OMR register is zero, the carry or borrow
is generated out of bit 35 of the result. If the CC bit in the OMR register is one, the carry or borrow is
generated out of bit 31 of the result. The carry bit is also modified by bit manipulation and shift
instructions. Otherwise, this bit is cleared.
5.1.8.2
Overflow (V)—Bit 1
If the CC bit in the OMR register is zero and if an arithmetic overflow occurs in the 36-bit result, the
overflow (V) bit (SR bit 1) is set. If the CC bit in the OMR register is one and an arithmetic overflow
occurs in the 32-bit result, the overflow bit is set. This indicates that the result is not representable in the
accumulator register and the accumulator register has overflowed. Otherwise, this bit is cleared.
5.1.8.3
Zero (Z)—Bit 2
The zero (Z) bit (SR bit 2) is set if the result equals zero. Otherwise, this bit is cleared. The number of bits
checked for the zero test depends on the OMR's CC bit and which instruction is executed, as documented
in Section 3.6, "Condition Code Generation," on page 3-33.
5.1.8.4
Negative (N)—Bit 3
If the CC bit in the OMR register is zero and if bit 35 of the result is set, the negative (N) bit (SR bit 3) is
set. If the CC bit in the OMR register is one and if bit 31 of the result is set, the negative bit is set.
Otherwise, this bit is cleared.
Mode Register (MR)
15
14
13
12
11
LF
*
*
*
*
Figure 5-4. Status Register Format
Program Controller
Architecture and Programming Model
Condition Code Register (CCR)
10
9
8
7
6
I1
I0
L
SZ
*
5
4
3
2
1
E
U
N
Z
V
AA0011
0
C
5-7

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