Motorola DSP56800 Manual page 303

DO
Operation upon Executing DO Instruction:
HWS[0] → HWS[1]; #xx → LC
PC → HWS[0]; LF → NL; expr → LA
1 → LF
HWS[0] → HWS[1]; S → LC
PC → HWS[0]; LF → NL; expr → LA
1 → LF
Operation When Loop Completes (End-of-Loop Processing):
NL → LF
HWS[1] → HWS[0]; 0 → NL
Description: Begin a hardware DO loop that is to be repeated the number of times specified in the instruction's
source operand, and whose range of execution is terminated by the destination operand (shown previ-
ously as "expr"). No overhead other than the execution of this DO instruction is required to set up this
loop. DO loops can receive their loop count as an immediate value or as a variable stored in an on-chip
register. When executing a DO loop, the instructions are actually fetched each time through the loop.
Therefore, a DO loop can be interrupted.
During the first instruction cycle, the DO instruction's source operand is loaded into the 13-bit LC reg-
ister, and the second location in the HWS receives the contents of the first location. The LC register
stores the remaining number of times the DO loop will be executed and can be accessed from inside
the DO loop as a loop count variable subject to certain restrictions. The DO instruction allows all reg-
isters on the DSP core to specify the number of loop iterations, except for the following: M01, HWS,
OMR, and SR. If immediate short data is instead used to specify the loop count, the 6 LSBs of the LC
register are loaded from the instruction, and the upper 7 MSBs are cleared.
During the second instruction cycle, the current contents of the PC are pushed onto the HWS. The DO
instruction's destination address (shown as "expr") is then loaded into the LA register. This 16-bit op-
erand is located in the instruction's 16-bit absolute address extension word (as shown in the opcode
section). The value in the PC pushed onto the HWS is the address of the first instruction following the
DO instruction (that is, the first actual instruction in the DO loop). At the bottom of the loop, when it
is necessary to return to the top for another loop pass, this value is read (that is, copied but not pulled)
from the top of the HWS and loaded into the PC.
During the third instruction cycle, the LF is set. The PC is repeatedly compared with LA to determine
if the last instruction in the loop has been fetched. If LA equals PC, the last instruction in the loop has
been fetched and the LC is tested. If LC is not equal to one, it is decremented by one, and SSH is loaded
into the PC to fetch the first instruction in the loop again. If LC equals one, the end-of-loop processing
begins.
During the end-of-loop processing, the NL bit is written into the LF, and the NL bit is cleared. The
contents of the second HWS location are written into the first HWS location. Instruction fetches now
continue at the address of the instruction that follows the last instruction in the DO loop.
DO loops can also be nested as shown in Section 8.6, "Loops," on page 8-20. When DO loops are nest-
ed, the end-of-loop addresses must also be nested and are not allowed to be equal. The assembler gen-
erates an error message when DO loops are improperly nested.
Start Hardware Do Loop
Instruction Set Details
Assembler Syntax:
DO #xx,expr
DO S,expr
DO
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