Motorola DSP56800 Manual page 335

MACR
Operation:
D + S1 * S2 + r → D (no parallel move)
D + S1 * S2 + r → D (one parallel move)
D + S1 * S2 + r → D (two parallel reads)
Description: Multiply the two signed 16-bit source operands (S1 and S2), add or subtract the product to or from the
specified 36-bit destination accumulator (D), and round the result using the specified rounding. The
rounded result is stored in the destination accumulator. (Refer to RND for more complete information
on the convergent rounding process.) The "-" sign option is used to negate the specified product prior
to accumulation. This option is not available when a single parallel move or two parallel reads are per-
formed. The default sign option is "+".
Usage:
This instruction is used for the multiplication, accumulation, and rounding of fractional data.
Example:
MACR
Before Execution
0 0003
A2 A1
Explanation of Example:
Prior to execution, the 16-bit X0 register contains the value $4000, the 16-bit Y1 register contains the
value $C000, and the 36-bit A accumulator contains the value $0:0003:8000. Execution of the
MACR -X0,Y1,A instruction multiplies the 16-bit signed value in the X0 register by the 16-bit
signed value in Y1 and subtracts the resulting 32-bit product from the 36-bit A accumulator, rounds
the result, and stores the result ($0:2004:0000) into the A accumulator. In this example, the default
rounding (convergent rounding) is performed.
Multiply-Accumulate and Round
Assembler Syntax:
MACR
MACR
MACR
-X0,Y1,A
8000
A0
X0
4000
Y1
C000
Instruction Set Details
(+)S1,S2,D(no parallel move)
S1,S2,D (one parallel move)
S1,S2,D (two parallel reads)
After Execution
0 2004
A2 A1
X0
Y1
MACR
0000
A0
4000
C000
A-105