Motorola DSP56800 Manual page 336

MACR
Condition Codes Affected:
15 14
LF *
See Section 3.6.5, "16-Bit Destinations," on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, "36-Bit Destinations—CC Bit Set," on page 3-34 and Section 3.6.4, "20-Bit Desti-
nations—CC Bit Set," on page 3-34 for the case when the CC bit is set.
Instruction Fields:
Operation
MACR
Data ALU Operation
Operation
MACR
A-106
Multiply-Accumulate and Round
MR
13 12 11 10 9
* * * * I1
SZ — Set according to the standard definition of the SZ bit (parallel move)
L — Set if limiting (parallel move) or overflow has occurred in result
E — Set if the signed integer portion of A or B result is in use
U — Set according to the standard definition of the U bit
N — Set if bit 35 of A or B result is set except during saturation
Z — Set if A or B result equals zero
V — Set if overflow has occurred in A or B result
Operands C
(±)Y1,X0,FDD 2
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
Registers
Y1,B1,F
Y0,Y0,F
Y0,A1,F
X0,Y0,F
X0,Y1,F
Y0,Y1,F
(F = A or B)
DSP56800 Family Manual
CCR
8 7 6 5 4 3
SZ L E U N
I0
W
1 Fractional MAC with round, multiplication result
optionally negated before addition.
Parallel Memory Read or Write
Memory Access Source or Destination
X:(Rn)+
X:(Rn)+N
MACR
2 1 0
Z V
C
Comments
X0
Y1
Y0
A
B
A1
B1