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ROR
Condition Codes Affected:
15
14
LF
*
Instruction Fields:
Operation
ROR
Timing:
2 oscillator clock cycles
Memory:
1 program word
Rotate Right
MR
13
12
11
10
9
*
*
*
*
I1
N
— Set if bit 31 of A or B result is set
Z
— Set if bits 31–16 of A or B result are zero
V
— Always cleared
C
— Set if bit 16 of A or B was set prior to the execution of the instruction
Operands
C
FDD
2
Instruction Set Details
CCR
8
7
6
5
4
I0 SZ
L
E
U
N
W
1
Rotate 16-bit register right by 1 bit through the carry
bit
ROR
3
2
1
0
Z
V
C
Comments
A-155
- Quick Links:
- Dsp56800 Family Architecture
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