Lsll - Motorola DSP56800 Manual

LSLL

Operation:
S1 << S2 → D
(no parallel move)
Description: Logically shift the first 16-bit source operand (S1) to the left by the value contained in the lowest 4 bits
of the second source operand (S2) and store the result in the destination register (D). The destination
must always be a 16-bit register.
Implementation Note:
This instruction is actually implemented by the assembler using the ASLL instruction. It will disas-
semble as ASLL.
Example:
LSLL
Before Execution
Explanation of Example:
Prior to execution, the Y1 register contains the value to be shifted ($AAAA) and the X0 register con-
tains the amount to shift by ($0004). The contents of the destination register are not important prior to
execution because they have no effect on the calculated value. The LSLL instruction logically shifts
the value $AAAA four bits to the left and places the result in the destination register Y1.
Condition Codes Affected:
15 14
LF *
Multi-Bit Logical Left Shift
Y1,X0,Y1
Y1
AAAA
X0
0004
MR
13 12 11 10 9
* * * * I1
N — Set if bit 15 of result is set except during saturation
Z — Set if the result in D is zero
Instruction Set Details
Assembler Syntax:
LSLL S1,S2,D
; left shift of 16-bit Y1 by X0
After Execution
CCR
8 7 6 5 4
I0 S L E U
LSLL
(no parallel move)
Y1
AAA0
X0
0004
3 2 1 0
N Z
V C
A-95