Condition Code Generation; 36-Bit Destinations-Cc Bit Cleared - Motorola DSP56800 Manual

3.6

Condition Code Generation

The DSP core supports many different arithmetic instructions for both word and long-word operations.
The flexible nature of the instruction set means that condition codes must also be generated correctly for
the different combinations allowed. There are three questions to consider when condition codes are
generated for an instruction:
• Is the arithmetic operation's destination an accumulator, or a 16-bit register or memory location?
• Does the instruction operate on the whole accumulator or only on the upper portion?
• Is the CC bit set in the program controller's OMR register?
The CC bit in the OMR register allows condition codes to be generated without an examination of the
contents of the extension register. This sets up a computing environment where there is effectively no
extension register because its contents are ignored. Typically, the extension register is most useful in DSP
operations. For the case of general-purpose computing, the CC bit is often set when the program is not
performing DSP tasks. However, it is possible to execute any instruction with the CC bit set or cleared,
except for instructions that use one of the unsigned condition codes (HS, LS, HI, or LO).
This section covers different aspects of condition code generation for the different instructions and
configurations on the DSP core. Note that the L, E, and U bits are computed the same regardless of the size
of the destination or the value of the CC bit:
• L is set if overflow occurs or limiting occurs in a parallel move.
• E is set if the extension register is in use (that is, if bits 35–31 are not all the same).
• U is set according to the standard definition of the U bit.
3.6.1 36-Bit Destinations—CC Bit Cleared
Most arithmetic instructions generate a result for a 36-bit accumulator. When condition codes are being
generated for this case and the CC bit is cleared, condition codes are generated using all 36 bits of the
accumulator. Examples of instructions in this category are ADC, ADD, ASL, CMP, MAC, MACR, MPY,
MPYR, NEG, NORM, and RND.
The condition codes for 36-bit destinations are computed as follows:
• N is set if bit 35 of the corresponding accumulator is set except during saturation. During a
saturation condition, the V (overflow) bit is set and the N bit is not set.
• Z is set if bits 35–0 of the corresponding accumulator are all cleared.
• V is set if overflow has occurred in the 36-bit result.
• C is set if a carry (borrow) has occurred out of bit 35 of the result.
Data Arithmetic Logic Unit
Condition Code Generation
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