Multiply-Accumulator (Mac) And Logic Unit; Barrel Shifter - Motorola DSP56800 Manual

Accessing an accumulator through its individual portions (A2, A1, A0, B2, B1, or B0) is useful for systems
and control programming. When accumulators are manipulated using their constituent components,
saturation and limiting are disabled. This allows for microcontroller-like 16-bit integer processing for
non-DSP purposes.
Section 3.2, "Accessing the Accumulator Registers," provides a complete discussion of the ways in which
the accumulators can be employed. A description of the data limiting and saturation features of the data
ALU is provided in Section 3.4, "Saturation and Data Limiting."
3.1.3

Multiply-Accumulator (MAC) and Logic Unit

The multiply-accumulator (MAC) and logic unit is the main arithmetic processing unit of the DSP. This is
the block that performs all multiplication, addition, subtraction, logical, and other arithmetic operations
except shifting. It accepts up to three input operands and outputs one 36-bit result of the form
EXT:MSP:LSP (extension:most significant product:least significant product). Arithmetic operations in the
MAC unit occur independently and in parallel with memory accesses on the CGDB, XDB2, and PDB. The
data ALU registers provide pipelining for both data ALU inputs and outputs. An input register may be
written by memory in the same instruction where it is used as the source for a data ALU operation. The
inputs of the MAC and logic unit can come from the X and Y registers (X0, Y1, Y0), the accumulators
(A1, B1, A, B), and also directly from memory for common instructions such as ADD and SUB.
The multiplier executes 16-bit x 16-bit parallel signed/unsigned fractional and 16-bit x 16-bit parallel
signed integer multiplications. The 32-bit product is added to the 36-bit contents either of the A or B
accumulator or of the 16-bit contents of the X0, Y0, or Y1 registers and then stored in the same register.
This multiply-accumulate is a single cycle operation (no pipeline). For integer multiplication, the 16 LSBs
of the product are stored in the MSP of the accumulator; the extension register is filled with sign extension
and the LSP of the accumulator remains unchanged.
If a multiply without accumulation is specified by a MPY or MPYR instruction, the unit clears the
accumulator and then adds the contents to the product. The results of all arithmetic instructions are valid
(sign extended) 36-bit operands in the form EXT:MSP:LSP (A2:A1:A0 or B2:B1:B0).
When a 36-bit result is to be stored as a 16-bit operand, the LSP can simply be truncated, or it can be
rounded into the MSP. The rounding performed is either the convergent rounding (round to the nearest
even) or two's-complement rounding. The type of rounding is specified by the rounding bit in the
operating mode register. See Section 3.5, "Rounding," for a more detailed discussion of rounding.
The logic unit performs the logical operations AND, OR, EOR, and NOT on data ALU registers. It is 16
bits wide and operates on data in the MSP of the accumulator. The least significant and EXT portions of
the accumulator are not affected. Logical operations can also be performed in the bit-manipulation unit.
The bit-manipulation unit is used when performing logical operations with immediate values and can be
performed on any register or memory location.
3.1.4

Barrel Shifter

The 16-bit barrel shifter performs single-cycle, 0- to 15-bit arithmetic or logical shifts of 16-bit data. Since
both the amount to be shifted as well as the value to shift come from registers, it is possible to shift data by
a variable amount. See Figure 3-3 on page 3-6. It is also possible to use this unit to right shift 32-bit values
using the ASRAC and LSRAC instructions, as demonstrated in Section 8.2, "16- and 32-Bit Shift
Operations," on page 8-8.
Data Arithmetic Logic Unit
Overview and Architecture
3-5