Table 6-14 Register Fields For General-Purpose Writes And Reads; Table 6-15 Address Generation Unit (Agu) Registers - Motorola DSP56800 Manual

In some cases, the notation used when specifying an accumulator determines whether or not saturation is
enabled when the accumulator is being used as a source in a move or parallel move instruction. Refer to
Section 3.4.1, "Data Limiter," on page 3-26 and Section 3.2, "Accessing the Accumulator Registers," on
page 3-7 for information.
Table 6-14. Register Fields for General-Purpose Writes and Reads
Register Field Registers in This Field
HHH A, B, A1, B1
HHHH A, B, A1, B1
DDDDD A, A2, A1, A0
B, B2, B1, B0
R0, R1, R2, R3
Table 6-15 shows the register set available for use as pointers in address-register-indirect addressing
modes. This table also shows the notation used for AGU registers in AGU arithmetic operations.
Table 6-15. Address Generation Unit (AGU) Registers
Registers in This
Register Field
Rn
Rj R0, R1, R2, R3
N
M01
Table 6-16 shows the register set available for use in data ALU arithmetic operations. The most common
field used in this table is FDD.
Seven data ALU registers—two accumulators, two 16-bit MSP
X0, Y0, Y1 portions of the accumulators, and three 16-bit data registers
Seven data ALU and five AGU registers
X0, Y0, Y1
R0-R3, N
All CPU registers
Y1, Y0, X0
N, SP
M01
OMR, SR
LA, LC
HWS
Field
R0–R3 Five AGU registers available as pointers for addressing and as
SP sources and destinations for move instructions
Four pointer registers available as pointers for addressing
N One index register available only for indexed addressing modes
M01 One modifier register
Instruction Set Introduction
DSP56800 Instruction Set Summary
Comments
Comments
6-15