Combined Jtag And Once Interface - Motorola DSP56800 Manual

Chapter 9
JTAG and On-Chip Emulation (OnCE™)
The DSP56800 family includes extensive integrated test and debug support. Two modules, the On-Chip
Emulation (OnCE) module and the test access port (TAP, commonly called the JTAG port) provide board-
and chip-level testing and software debugging capability. Both are accessed through a common
JTAG/OnCE interface. Using these modules allows the user to insert the DSP chip into a target system
while retaining debug control. This capability is especially important for devices without an external bus,
since it eliminates the need for a costly cable to bring out the footprint of the chip, as required by a
traditional emulator system.
The OnCE port is a Motorola-designed module used to debug application software used with the chip. The
port is a separate on-chip block that allows non-intrusive interaction with the DSP and is accessible
through the pins of the JTAG interface. The OnCE port makes it possible to examine contents of registers,
memory, or on-chip peripherals in a special debug environment. No user-accessible resources need be
sacrificed to perform debugging operations.
The JTAG port conforms to the IEEE Standard Test Access Port and Boundary-Scan Architecture
specification (IEEE 1149.1a-1993) as defined by the Joint Test Action Group (JTAG). The JTAG module
uses a boundary scan technique to test the interconnections between integrated circuits after they are
assembled onto a printed circuit board. Using a boundary scan allows a tester to observe and control signal
levels at each component pin through a special register coupled to each pin, called a boundary scan cell.
This is important for testing continuity and determining if pins are stuck at a one or zero level.
This chapter presents an overview of the capabilities of the JTAG and OnCE modules. Since their
operation is highly dependent upon the architecture of a specific DSP56800 device, the exact
implementation is necessarily device dependant. For more complete information on interfacing, the debug
and test commands available, and other implementation details, consult the appropriate device's user's
manual.
9.1

Combined JTAG and OnCE Interface

The JTAG and OnCE modules are tightly coupled. The JTAG port provides the interface for both modules
and handles communications with host development and test systems. Figure 9-1 on page 9-2 shows a
block diagram of the JTAG/OnCE modules and external host interface.
JTAG and On-Chip Emulation (OnCE™) 9-1