Motorola DSP56800 Manual page 389

SBC
Operation:
D - S - C → D
(no parallel move)
Description: Subtract the source operand (S) and C of the CCR from the destination operand (D) and store the result
in the destination accumulator. Long words (32 bits) are subtracted from the 36-bit destination accu-
mulator.
Usage:
This instruction is typically used in multi-precision subtraction operations (see Section 3.3.8.1,
"Multi-Precision Addition and Subtraction," on page 3-23) when it is necessary to subtract two num-
bers that are larger than 32 bits, such as 64-bit or 96-bit subtraction.
Example:
SBC
Before Execution
0 4000
A2 A1
Y 3FFF
Y1
Explanation of Example:
Prior to execution, the 32-bit Y register (comprised of the Y1 and Y0 registers) contains the value
$3FFF:FFFE, and the 36-bit accumulator contains the value $0:4000:0000. In addition, C is set to one.
The SBC instruction automatically sign extends the 32-bit Y registers to 36-bits and subtracts this val-
ue from the 36-bit accumulator. In addition, C is subtracted from the LSB of this 36-bit addition. The
36-bit result is stored back in the A accumulator, and the conditions codes are set correctly. The Y1:Y0
register pair is not affected by this instruction.
Note:
C is set correctly for multi-precision arithmetic using long-word operands only when the extension reg-
ister of the destination accumulator (A2 or B2) contains sign extension of bit 31 of the destination ac-
cumulator (A or B).
Subtract Long with Carry
Assembler Syntax:
SBC
Y,A
0000
A0
FFFE
Y0
SR
0301
Instruction Set Details
S,D (no parallel move)
After Execution
0 0000
A2 A1
Y 3FFF
Y1
SR
SBC
0001
A0
FFFE
Y0
0310
A-159